PXI-5404 Datasheet, PDF (3/6 Pages) National Instruments Corporation – 9 kHz to 105 MHz sine wave/DC to 100 MHz clock/1.07 μHz frequency resolution

100 MHz Frequency Generator
Software
If you want to build an automated test application or integrate the
PXI-5404 in your test software, use the IVI-compliant NI-FGEN
instrument driver with:
• NI LabVIEW
• Microsoft Visual Basic
•NI LabWindows/CVI
•Microsoft Visual C/C++
Interactive Control
The PXI-5404 comes with the versatile Sources Soft Front Panel
with which you can interactively control the PXI-5404. You can
generate sine and clock outputs with control of frequency, phase,
amplitude, and duty cycle with the Sources Soft Front Panel.
Furthermore, you can run the PXI-5404 in simulation mode from
the Sources Soft Front Panel.
NI-FGEN comes with a comprehensive set of examples that
illustrate the programming and features of the PXI-5404 in all four
programming environments. Because NI-FGEN offers simulation
mode, you can run your application on a laptop PC, for example.
Thanks to this feature, you can develop your application with the
PXI-5404 remotely or a team of developers can work on an
application without the need for hardware in their systems.
Ordering Information
NI PXI-5404 ................................................778577-01
Includes the module, NI-FGEN, Sources Soft Front Panel,
and calibration certificate.
Specifications
Specifications are valid for the Operating
Temperature Range, unless otherwuse noted.
Output Characteristics
Number of outputs .................................... 1 sine and 1 clock,
Both generate same frequency
simultaneously.
CH0 SINE (Channel 0 Sine Wave Output, I/O Panel Connector)
Connector .................................................. SMB
Frequency Range ....................................... 9 kHz to 105 MHz
Frequency Resolution ................................ 1.07 µHz
Phase Range .............................................. 0 to 359.978 deg
Phase Resolution ....................................... 16384 steps including endpoints
(approximately 0.022 deg)
Output Impedance ..................................... 50 Ω ±4% (9 kHz to 105 MHz)
Output Protection ...................................... 10 Vrms
Sampling Rate............................................ 300 MS/s
Amplitude Range
Open load ............................................. 4.00 Vpp to 2.00 Vpp
50 Ω load .............................................. 2.00 Vpp to 1.00 Vpp
Amplitude Resolution ................................ 2048 steps including endpoints
(Open Load: Approximately 977 µV.
50 Ω Load: Approximately 489 µV)
Amplitude Accuracy ................................... ±1% @ 50 kHz
Amplitude Passband Flatness.................... ±0.2 dB relative to the amplitude @
50 kHz, 9 kHz < f <105 MHz
Amplitude Temperature Coefficient........... ±0.013% / ºC
Vertical Resolution ..................................... 12 bits @ 4 Vpp (open load)
11 bits @ 2 Vpp (open load)
Bandwitdth................................................. 105 MHz (0.2 dB)
Filter ........................................................... Analog 7-pole elliptical
SINAD
SFDR
THD
Average Noise
Density
1 MHz
+ 51 dB
10 MHz
+ 48 dB
20 MHz
+ 45 dB
50 MHz
+ 42 dB
100 MHz
+ 42 dB
1 MHz
- 55 dBc
10 MHz
- 54 dBc
20 MHz
- 49 dBc
50 MHz
- 45 dBc
100 MHz
- 53 dBc
1 MHz
- 56 dB
10 MHz
- 52 dB
20 MHz
- 48 dB
50 MHz
- 41 dB
100 MHz
- 36 dB
0.126 µVrms / √Hz
- 125 dBm / Hz
Amplitude set to 1.8 Vpp (~ –1 dBFS).
Measured from 9 kHz to 150 MHz.
Amplitude 1.8 Vpp (~ –1 dBFS).
Measured from 9 kHz to 150 MHz
Includes harmonics.
Amplitude 1.8 Vpp (~ –1 dBFS).
Includes 2nd through the 6th harmonic.
Integrated from 9 kHz to 150 MHz
CH0 CLOCK (Channel 0 Clock Output, I/O Panel Connector)
Connector .................................................. SMB
Frequency Range ....................................... DC to 105 MHz
Frequency Resolution ................................ 1.07 µHz
Phase Range .............................................. 0 to 359.978 deg
Phase Resolution ....................................... 16384 steps including endpoints
Output Impedance ..................................... 50 Ω ±12%, (DC to 105 MHz)
Output Protection ...................................... +8 to -4 V
Output
Current
Amplitude
(Open Load)
VOL
VOH
Amplitude
(50 Load)
VOL
VOH
5.0 V Level 3.3 V Level 1.8 V Level
120 mA
72 mA
48 mA
5.0 V Level 3.3 V Level 1.8 V Level
Min Max Min Max Min Max
-0.10 V 0.40 V -0.10 V 0.40 V -0.10 V 0.40 V
4.00 V 5.30 V 2.60 V 3.70 V 1.40 V 2.20 V
5.0 V Level 3.3 V Level 1.8 V Level
Min Max Min Max Min Max
-0.10 V 0.20 V -0.10 V 0.20 V -0.10 V 0.20 V
2.00 V 2.65 V 1.30 V 1.85 V 0.70 V 1.10 V
Typical
Source or Sink
If the CH0 CLOCK out signal
is terminated into a 50 Ω load
the voltage levels will be
divided by two.
Rise/Fall Time............................................. 4 ns
Duty Cycle Range ...................................... 25 to 75%
Duty Cycle Accuracy ................................. (Typical 1.07 µHz to 60 MHz)
30 to 70%.................................. ±2%
25 and 75% ............................... ±3%
PFI 0 (Programmable Function Interface, I/O Panel Connector)
Connector .................................................. SMB
Direction ................................................... Bidirectional
Frequency Range ....................................... DC to 20 MHz
As an Input
Destination for Input Signal ....................... 1. PXI_Trig <0:7>
( Backplane Connector )
2. REF OUT (I/O Panel
SMB Connector)
3. Start Trigger
Input Resistance ........................................ 1 kΩ ±1%
Input Protection ......................................... +8 to -4
VIH
................................................... 2.0 V
VIL
................................................... 0.8 V
Output Protection ...................................... +8 to -4V
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