UPD9611 Datasheet, PDF (9/28 Pages) NEC – FOUR-CHANNEL PCM CODEC

µPD9611
(5) Control of SPDATA pin
If SPSYNC pin is set to the high level in synchronization with the rising edge (↑) of the data clock applied
to the SPCLK pin, data of the SPDATA pin is latched by the falling edge (↓) of the data clock and
consecutively fetched in.
After the 8-bit data has been fetched, the setting operation is performed according to the data.
This setting operation is performed during the 8 clocks after fetching the data and the next data is valid
at the 17th clock.
Therefore, when setting 1 word (8 bits) of data, input 17 clocks or more to the SPCLK pin.
SPSYNC
SPCLK 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
SPDATA
Data fetch
Don’t care
Setting operation
Setting
completed
(The next
data is valid.)
Ensure that 17 clocks or more are input to the SPCLK pin between the rising of SPSYNC and the rising of
the next SPSYNC.
SPSYNC
SPCLK
17 clocks or more
9