UPD9611 Datasheet, PDF (4/28 Pages) NEC – FOUR-CHANNEL PCM CODEC

µPD9611
1. PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Symbol I/O
Name and Function
AIN1
I Transmit analog input pin for channel 1
When not used, connect to ACOMOUT1 pin.
AOUT1
O Receive analog output pin for channel 1
NC
– Leave this pin open.
AIN2
I Receive analog input pin for channel 2
When not used, connect to ACOMOUT1 pin.
AOUT2
O Transmit analog output pin for channel 2
NC
– Leave this pin open.
ACOMIN1
I Signal reference voltage input for channel 1
ACOMOUT1 O Signal reference voltage output for channel 1
ACOMIN2
I Signal reference voltage input for channel 2
ACOMOUT2 O Signal reference voltage output for channel 2
AVDD1
– Analog power supply pin for channel 1 +5 ± 0.25 V
AVDD2
– Analog power supply pin for channel 2 +5 ± 0.25 V
AVDD3
– Analog power supply pin for channel 3 +5 ± 0.25 V
AVDD4
– Analog power supply pin for channel 4 +5 ± 0.25 V
DVDD
– Digital power supply pin
+5 ± 0.25 V
NC
– Leave this pin open.
PD1
I Power-down control input pin for channel 1
Channel 1 enters power-down mode when this signal is low level.
The output of DX pin for channel 1 becomes high-impedance and AOUT1 becomes
signal reference voltage in the power-down mode.
PD2
I Power-down control input pin for channel 2
Channel 2 enters power-down mode when this signal is low level.
The output of DX pin for channel 2 becomes high-impedance and AOUT2 becomes
signal reference voltage in the power-down mode.
PD3
I Power-down control input pin for channel 3
Channel 3 enters power-down mode when this signal is low level.
The output of DX pin for channel 3 becomes high-impedance and AOUT3 becomes
signal reference voltage in the power-down mode.
PD4
I Power-down control input pin for channel 4
Channel 4 enters power-down mode when this signal is low level.
The output of DX pin for channel 4 becomes high-impedance and AOUT4 becomes
signal reference voltage in the power-down mode.
FSC
I Frame synchronous clock input pin (8 kHz)
DCLK
I Data clock input pin (2048 kHz)
DX
O Transmit PCM data output pin
This pin outputs PCM data for channel 1 to 4 in synchronization with rising edges
of DCLK after rising edges of FSC. It becomes high-impedance for other timings.
DR
I Receive PCM data input pin
This pin inputs PCM data for channel 1 to 4 in synchronization with falling edges of
DCLK after rising edges of FSC.
SPCLK
I Setting data clock input pin
SPSYNC
I Setting synchronous clock input pin
SPDATA
I Setting data input pin
4