UPD9611 Datasheet, PDF (7/28 Pages) NEC – FOUR-CHANNEL PCM CODEC

µPD9611
3. GENERAL OPERATION
(1) PCM data transfer
In the transmit section, if FSC pin is set to the high level in synchronization with the rising edge (↑) of
the data clock applied to the DCLK pin, the DX pin becomes active and sign bit data (MSB) of channel
1 is output. The following data of 7 bits is clocked out in synchronization with the rising edge (↑) of each
data clock. Sign bit data (MSB) of channel 2 is output in synchronization with the rising edge (↑) of the
9th data clock. In the same manner, each data up to channel 4 is output and the rising edge (↑) of the
33rd data clock then sets the DX pin to high-impedance state.
Similarly, in the receive section, if the FSC pin is set to the high level in synchronization with the rising
edge (↑) of the data clock applied to the DCLK pin, data of DR pin is latched by the falling edges (↓) of
the data clock and consecutively clocked in.
(2) Power down control
The µPD9611 has the following two methods for power down control and is able to control power-down
independently for each channel.
• Sets pins PD1 to PD4 to high or low level.
• Inputs 8-bit setting data from SPDATA pin (see (5) Control of SPDATA pin).
Internal data is the logical sum of PD1 to PD4 pin state and 8-bit setting data input.
If the internal data is 0, the channel enters the power-down state. If the internal data is 1, the channel
enters the power-up state. In the power down state, PCM data in the channel goes to high-impedance
state and analog output becomes the signal reference voltage level.
8-Bit Setting Data
(Channel 1)
0
1
0
1
PD1 Pin
0
0
1
1
Internal Data
0
1
1
1
Remarks 1. 0: Power down, 1: Power up
2. The settings are the same for channel 2 to channel 4.
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