UPD753108 Datasheet, PDF (87/459 Pages) NEC – 4-bit Single-chip Microcontrollers

CHAPTER 4 INTERNAL CPU FUNCTIONS
Figure 4-10. Data Saved in Stack Memory (Mk I mode)
PUSH instruction
Stack
CALL, CALLF instruction
Stack
Interrupt
Stack
SP – 2 ^{Register pair low order}
SP – 1 Register pair high order
SP
SP – 4
PC11 to PC8
SP – 3
MBE
RBE
0^{Note 1}
Note
PC12
2
SP – 2
PC3 to PC0
SP – 1
PC7 to PC4
SP
SP – 6
PC11 to PC8
SP – 5
MBE
RBE
0^{Note 1}
Note 2
PC12
SP – 4
PC3 to PC0
SP – 3
PC7 to PC4
SP – 2 IST1 IST0 MBE RBE
PSW
SP – 1 CY SK2 SK1 SK0
SP
Figure 4-11. Data Restored from Stack Memory (Mk I mode)
POP instruction
Stack
SP Register pair low order
SP+1 Register pair high order
SP+2
RET, RETS instruction
Stack
SP
PC11 to PC8
SP+1
MBE
RBE
0^{Note 1}
Note 2
PC12
SP+2
PC3 to PC0
SP+ 3
PC7 to PC4
SP+4
RETI instruction
Stack
SP
PC11 to PC8
SP+1
MBE
RBE
0^{Note 1}
Note 2
PC12
SP+2
PC3 to PC0
SP+3
PC7 to PC4
SP+4 IST1 IST0 MBE RBE
PSW
SP+5 CY SK2 SK1 SK0
SP+6
Notes 1. For the µPD75P3116, PC13 is saved to this position.
2. For the µPD753104, PC12 is set to 0.
87