UPD753108 Datasheet, PDF (272/459 Pages) NEC – 4-bit Single-chip Microcontrollers

CHAPTER 5 PERIPHERAL HARDWARE FUNCTION
Address 7
F8CH
0
Figure 5-102. Display Mode Register Format
6
5
4
3
2
1
0 Symbol
0 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0 LCDM
LCD clock selection
LCDM5
LCDM4
0
0
0
1
1
0
1
1
LCDCL^Note
fW/2⁹ (64 Hz)
fW/2⁸ (128 Hz)
fW/2⁷ (256 Hz)
fW/2⁶ (512 Hz)
Note LCDCL is supplied only when the watch timer operates. To use the LCD controller, bit 2 of watch mode
register WM should be set to 1.
Display mode selection
LCDM3
LCDM2
LCDM1
LCDM0
0
×
×
×
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
Other than the above
Note All segment signals are unselected.
Time Division _{Bias Method}
Value
Display off ^Note
4
1/3
3
1/3
2
1/2
3
1/2
Static
Setting prohibited
Frame frequency (Hz)
Display Duty
Static
1/2
1/3
LCDCL
1/4
fW/2⁹
(64 Hz)
64
32
21
16
fW/2 ⁸
(128 Hz)
128
64
43
32
When fW = 32.768 kHz
fW : Input clock to watch timer (fX/128 or fXT)
fW/2⁷
(256 Hz)
256
128
85
64
fW/2⁶
(512 Hz)
512
256
171
128
272