UPD753108 Datasheet, PDF (326/459 Pages) NEC – 4-bit Single-chip Microcontrollers

CHAPTER 6 INTERRUPT FUNCTION AND TEST FUNCTION
(6) Executing pending interrupt – interrupt occurs during interrupt processing
(INTBT has higher priority and INTT0 and INTCSI have lower priority) –
<Main routine>
Reset
EI IEBT
EI IET0
EI IECSI
MOV A, #9
MOV IPS, A
INTT0
<1>
INTBT
<INTBT processing routine>
PUSH rp
<2> INTCSI
POP rp
<3> RETI
<INTCSI processing routine>
<4> RETI
<INTT0 processing routine>
RETI
<1> If INTBT with the higher priority and INTT0 with the lower priority occur at the same time, the processing
of the interrupt with the higher priority is started (if there is no possibility that an interrupt with the higher
priority occurs while another interrupt with the higher priority is processed, DI IE×× is not necessary).
<2> If an interrupt with the lower priority occurs while the interrupt with the higher priority is executed, the
interrupt with the lower priority is kept pending.
<3> When the interrupt with the higher priority has been processed, INTCSI with the higher priority of the
pending interrupts is executed.
<4> When the processing of INTCSI has been completed, the pending INTT0 is processed.
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