UPD753108 Datasheet, PDF (282/459 Pages) NEC – 4-bit Single-chip Microcontrollers

CHAPTER 5 PERIPHERAL HARDWARE FUNCTION
5.7.8 Supply of LCD drive power VLC0, VLC1, and VLC2
In the µPD753108, a split resistor can be incorporated in the VLC0 to VLC2 pins for the LCD drive power supply.
According to the bias method, the LCD drive power can be supplied without an external split resistor. The
µPD753108 also includes the BIAS pin to deal with various LCD drive voltages. The BIAS and VLC0 pins are
connected externally.
Table 5-18 lists proper LCD drive power supply values based on the static, 1/2, and 1/3 bias methods.
Table 5-18. LCD Drive Power Supply Values
Bias Method
LCD Drive Power
VLC0
VLC1
VLC2
VSS
No Bias
(Static Mode)
VLCD
2/3VLCD
1/3VLCD
0V
1/2
V LCD
1/2VLCD^Note
0V
1/3
VLCD
2/3VLCD
1/3VLCD
0V
Note When 1/2 bias is used, the VLC1 and VLC2 pins must be connected
externally.
Remark When the BIAS and VLC0 pins are not connected, VLCD = 3/5VDD
(internal split resistor must be specified by using a mask
option).
When the BIAS and VLC0 pins are connected, VLCD = VDD.
Figure 5-111, (a) to (c) show LCD drive power supply examples according to Table 5-18.
Current flow through the split resistor can also be cut by clearing display control register bit 0 (LCDC0).
This LCD power on/off control is also useful to prevent DC voltage from being applied to LCD (if the system clock
subsystem is selected) when the LCD clock is stopped by execution of a STOP instruction, when the watch timer
operates using the main system clock. That is, display control register bit 0 (LCDC0) is cleared and all LCD drive
power sources are placed in the same potential VSS immediately before the STOP instruction is executed, thereby
suppressing the potential difference between the LCD electrodes even if the LCD clock is stopped. When the watch
timer operates by using the subsystem clock, the LCD display can be connected.
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