UPD70F3116 Datasheet, PDF (726/826 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 15 RESET FUNCTION
Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (6/6)
On-Chip Hardware
On-chip
peripheral
I/O
A/D converter
Port function
NBD function
Flash memory
Register Name
A/D voltage detection mode register n (ADETMn) (n = 0, 1)
A/D voltage detection mode register nL (ADETMnL) (n = 0, 1)
A/D voltage detection mode register nH (ADETMnH) (n = 0, 1)
A/D conversion result register 0n (ADCR0n) (n = 0 to 7)
A/D conversion result register 1n (ADCR1n) (n = 0 to 7)
A/D internal trigger selection register (ITRG0)
Ports (P0 to P4, PDH, PCS, PCT, PCM)
Port (PDL)
Port (PDLL)
Port (PDLH)
Mode registers (PM1 to PM4, PMDH, PMCS, PMCT, PMCM)
Mode register (PMDL)
Mode register (PMDLL)
Mode register (PMDLH)
Mode control registers (PMC1 to PMC4)
Mode control registers (PMCDH, PMCCS)
Mode control register (PMCDL)
Mode control register (PMCDLL)
Mode control register (PMCDLH)
Mode control register (PMCCT)
Mode control register (PMCCM)
Function control registers (PFC1, PFC2)
RAM access data buffer register L (NBDL)
RAM access data buffer register LL (NBDLL)
RAM access data buffer register LU (NBDLU)
RAM access data buffer register H (NBDH)
RAM access data buffer register HL (NBDHL)
RAM access data buffer register HU (NBDHU)
DMA source address setting register SL (NBDMSL)
DMA source address setting register SH (NBDMSH)
DMA destination address setting register DL (NBDMDL)
DMA destination address setting register DH (NBDMDH)
Flash programming mode control register (FLPMC)
Initial Value After Reset
0000H
00H
00H
0000H
0000H
00H
Undefined
Undefined
Undefined
Undefined
FFH
FFFFH
FFH
FFH
00H
00H/FFH
0000H/FFFFH
00H/FFH
00H/FFH
00H/53H
00H/0FH
00H
0000H
00H
00H
0000H
00H
00H
Undefined
Undefined
Undefined
Undefined
08H/0CH/00H^Note
Note µPD703116: 00H
µPD70F3116: 08H or 0CH (For details, refer to 16.7.12 Flash programming mode control register
(FLPMC).)
Caution
In the table above, “Undefined” means either undefined at the time of a power-on reset or
undefined due to data destruction when RESET ↓ input and data write timing are synchronized.
On a RESET ↓ other than this, data is maintained in its previous status.
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User’s Manual U14492EJ5V0UD