UPD70F3116 Datasheet, PDF (412/826 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 10 SERIAL INTERFACE FUNCTION
10.2.2 Configuration
UART0 is controlled by asynchronous serial interface mode register 0 (ASIM0), asynchronous serial interface
status register 0 (ASIS0), and asynchronous serial interface transmit status register 0 (ASIF0). Receive data is
maintained in receive buffer register 0 (RXB0), and transmit data is written to transmit buffer register 0 (TXB0).
Figure 10-1 shows the configuration of asynchronous serial interface 0 (UART0).
(1) Asynchronous serial interface mode register 0 (ASIM0)
The ASIM0 register is an 8-bit register for specifying the operation of the asynchronous serial interface.
(2) Asynchronous serial interface status register 0 (ASIS0)
The ASIS0 register consists of a set of flags that indicate the error contents when a reception error occurs.
The various reception error flags are set (1) when a reception error occurs and are reset (0) when the ASIS0
register is read.
(3) Asynchronous serial interface transmit status register 0 (ASIF0)
The ASIF0 register is an 8-bit register that indicates the status when a transmit operation is performed.
This register consists of a transmit buffer data flag, which indicates the hold status of TXB0 data, and the
transmit shift register data flag, which indicates whether transmission is in progress.
(4) Reception control parity check
The receive operation is controlled according to the contents set in the ASIM0 register. A check for parity
errors is also performed during a receive operation, and if an error is detected, a value corresponding to the
error contents is set in the ASIS0 register.
(5) Receive shift register
This is a shift register that converts the serial data that was input to the RXD0 pin to parallel data. One byte
of data is received, and if a stop bit is detected, the receive data is transferred to receive buffer register 0
(RXB0).
This register cannot be directly manipulated.
(6) Receive buffer register 0 (RXB0)
This is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the
MSB.
During a reception enabled state, receive data is transferred from the receive shift register to the RXB0
register, synchronized with the end of the shift-in processing of one frame.
Also, the reception completion interrupt request (INTSR0) is generated by the transfer of data to the RXB0
register.
(7) Transmit shift register
This is a shift register that converts the parallel data that was transferred from transmit buffer register 0
(TXB0) to serial data.
When one byte of data is transferred from the TXB0 register, the shift register data is output from the TXD0
pin.
The transmission completion interrupt request (INTST0) is generated synchronized with the completion of
transmission of one frame.
This register cannot be directly manipulated.
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User’s Manual U14492EJ5V0UD