UPD70F3116 Datasheet, PDF (115/826 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 4 BUS CONTROL FUNCTION
(2) Address wait control register (AWC)
In the V850E/IA1, address setup wait and address hold wait states can be inserted before and after the T1
cycle, respectively.
These wait states can be set for each CS space via the AWC register.
This register can be read/written in 16-bit units.
Caution Write to the AWC register after reset, and then do not change the set values.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address Initial value
AWC AHW7 ASW7 AHW6 ASW6 AHW5 ASW5 AHW4 ASW4 AHW3 ASW3 AHW2 ASW2 AHW1 ASW1 AHW0 ASW0 FFFFF488H 0000H
CSn signal CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
Bit position Bit name
15, 13, 11, 9, AHWn
7, 5, 3, 1
(n = 0 to 7)
14, 12, 10, 8, ASWn
6, 4, 2, 0
(n = 0 to 7)
Function
Sets the insertion of an address hold wait state in each CSn space after the T1 cycle.
0: Address hold wait state not inserted
1: Address hold wait state inserted
Sets the insertion of an address setup wait state in each CSn space before the T1 cycle.
0: Address setup wait state not inserted
1: Address setup wait state inserted
User’s Manual U14492EJ5V0UD
115