UPD70F3116 Datasheet, PDF (298/826 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/COUNTER FUNCTION
(b) Up/down counter mode (UDC mode)
In the UDC mode, TM1n functions as a 16-bit up/down counter, counting based on the TCUD1n and
TIUD1n input signals.
This mode is divided into the UDC mode A and UDC mode B, depending on the condition of clearing
TM1n.
The conditions for clearing the TM1n are classified as follows depending on the operation mode.
Table 9-5. Timer 1 (TM1n) Clear Conditions
Operation Mode
General-purpose
timer mode
UDC mode A
TUMn Register
CMD
Bit
MSEL
Bit
0
0
1
0
UDC mode B
1
1
Settings other than the above
TMC1n Register
ENMD CLR1
Bit
Bit
CLR0
Bit
0
×
×
1
×
×
×
0
0
×
0
1
×
1
0
×
1
1
×
×
×
TM1n Clear
Clearing not performed (free-running timer)
Cleared upon match with CM1n0 set value
Cleared only by TCLR1n input
Cleared upon match with CM1n0 set value during up-
count operation
Cleared by TCLR1n input or upon match with CM1n0 set
value during up-count operation
Clearing not performed
Cleared upon match with CM1n0 set value during up-
count operation or upon match with CM1n1 set value
during down-count operation
Setting prohibited
Remarks 1. n = 0, 1
2. ×: Indicates that the set value of that bit is ignored.
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User’s Manual U14492EJ5V0UD