UPD784044 Datasheet, PDF (72/90 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLER

µPD784044(A), 784046(A)
(3) Electrical specifications of µPD784044(A2), 784046(A2) (4/6)
AC Characteristics (TA = –40 to +125 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Read/write operation
Parameter
System clock cycle time
Address setup time (vs. ASTB↓)
Address hold time (vs. ASTB↓)
ASTB high-level width
Address→RD↓ delay time
RD↓→address float time
Address→data input time
RD↓→data input time
ASTB↓→RD↓ delay time
Data hold time (vs. RD↑)
RD↑→address active time
RD low-level width
Address→LWR, HWR↓ delay time
LWR, HWR↓→data output time
ASTB↓→LWR, HWR↓ delay time
Data setup time (vs. LWR, HWR↑)
Data hold time (vs. LWR, HWR↑)
LWR, HWR↑→ ASTB↑ delay time
LWR, HWR low-level width
Address→WAIT↓ input time
ASTB↓→WAIT↓ input time
ASTB↓→WAIT hold time
ASTB↓→WAIT↑ delay time
RD↓→WAIT↓ input time
RD↓→WAIT hold time
RD↓→WAIT↑ delay time
LWR, HWR↓→WAIT↓ input time
LWR, HWR↓→WAIT hold time
LWR, HWR↓→WAIT↑ delay time
Symbol
tCYK
tSAST
tHSTA
tWSTH
tDAR
tFRA
tDAID
tDRID
tDSTR
tHRID
tDRA
tWRL
tDAW
tDWOD
tDSTW
tSODW
tHWOD
tDWST
tWWL
tDAWT
tDSTWT
tHSTWT
tDSTWTH
tDRWT
tHRWT
tDRWTH
tDWWT
tHWWT
tDWWTH
Expression
(0.5 + a) T – 20
0.5T – 20
(0.5 + a) T – 17
(1 + a) T – 15
(2.5 + a + n) T – 56
(1.5 + n) T – 53
0.5T – 16
0.5T – 14
(1.5 + n) T – 30
(1 + a) T – 15
0.5T – 16
(1.5 + n) T – 25
0.5T – 14
1.5T – 15
(1.5 + n) T – 36
(2 + a) T – 50
1.5T – 40
(1.5 + n) T + 5
(1.5 + n) T – 40
T – 40
(1 + n) T + 5
(1 + n) T – 40
T – 40
(1 + n) T + 5
(1 + n) T – 40
Note Specification when an external wait is inserted
MIN.
MAX.
Unit
100
250
ns
30
ns
30
ns
33
ns
85
ns
0
ns
194
ns
97
ns
34
ns
0
ns
36
ns
120
ns
85
ns
15
ns
34
ns
125
ns
36
ns
135
ns
114
ns
150
ns
110
ns
155
ns
210^Note
ns
60
ns
105
ns
160^Note
ns
60
ns
105
ns
160^Note
ns
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency)
2. a = 1 when an address wait is inserted, otherwise, 0.
3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or program-
mable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH).
4. Calculate values in the expression column with the system clock cycle time to be used because
these values depend on the system clock cycle time (tCYK = T). The values in the above expression
column are calculated based on T = 100 ns.
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