UPD17704 Datasheet, PDF (6/356 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

BLOCK DIAGRAM
P0A0-P0A3 4
P0B0-P0B3 4
P0C0-P0C3 4
P0D0-P0D3 4
P1A0-P1A3 4
P1B0-P1B3 4
P1C0-P1C3 4
P1D0-P1D3 4
Port
P2A0-P2A2 3
P2B0-P2B3 4
P2C0-P2C3 4
P2D0-P2D2 3
P3A0-P3A3 4
P3B0-P3B3 4
P3C0-P3C3 4
P3D0-P3D3 4
AD0/P0D0
AD1/P0D1
AD2/P0D2
AD3/P0D3
AD4/P1C2
AD5/P1C3
PWM0/P1B0
PWM1/P1B1
PWM2/P1B2
A/D
Converter
D/A
Converter
8-bit
Timer3
GND0-GND2
Basic
Timer
µPD17704, 17705, 17707, 17708, 17709
RF
RAM
672 × 4 bits
( µPD17704, 17705)
1120 × 4 bits
( µPD17707, 17708)
1776 × 4 bits
( µPD17709)
SYSREG
ALU
Instruction
Decoder
ROM
8192 × 16 bits
( µPD17704)
12288 × 16 bits
( µPD17705, 17707)
16384 × 16 bits
( µPD17708, 17709)
Program Counter
Stack
CPU
Peripheral
PLL
Serial
Interface0
Serial
Interface1
BEEP
Interrupt
Control
Frequency
Counter
8-bit
Timer0
Gate
Counter
8-bit
Timer1
8-bit
Timer2
OSC
Reset
VCOH
VCOL
EO0
EO1
SO0/P0A0
SCK0/P0A1
SCL/P0A2
SDA/P0A3
SI0/P0B3
SCK1/P0B2
SO1/P0B1
SI1/P0B0
BEEP0/P1D0
BEEP1/P1D1
INT0
INT1
INT2
INT3/P1A2
INT4/P1A3
FCG0/P2A0
FCG1/P2A1
FMIFC/P1C0
AMIFC/P1C1
TM0G/P1A0
XIN
XOUT
CE
RESET
VDD0, VDD1
VCPU
Regulator
REG
6