UPD17704 Datasheet, PDF (255/356 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

µPD17704, 17705, 17707, 17708, 17709
17. PLL FREQUENCY SYNTHESIZER
The PLL (Phase Locked Loop) frequency synthesizer is used to lock a frequency in the MF (Medium Frequency),
HF (High Frequency), andVHF (Very High Frequency) to a constant frequency by means of phase difference comparison.
17.1 Outline of PLL Frequency Synthesizer
Figure 17-1 outlines the PLL frequency synthesizer. A PLL frequency synthesizer can be configured by connecting
an external lowpass filter (LPF) and voltage controlled oscillator (VCO).
The PLL frequency synthesizer divides a signal input from the VCOH or VCOL pin by using a programmable divider
and outputs a phase difference between this signal and a reference frequency from the EO0 and EO1 pins.
The PLL frequency synthesizer operates only while the CE pin is high. It is disabled when the CE pin is low. For
the details of the disabled status of the PLL frequency synthesizer, refer to 17.5 PLL Disabled Status.
Figure 17-1. Outline of PLL Frequency Synthesizer
VCOH
VCOL
Input select
block
DBF
PLLSCNF flag
Programmable
divider (PD)
Phase
comparator
(^φ -DET)
4.5 MHz
Reference
frequency
generator
Unlock FF
Charge
pump
EO1
EO0
Note
Lowpass filter
(LPF)
Note
Voltage controlled
oscillator (VCO)
PLLMD1 flag
PLLMD0 flag
PLLRFCK3 flag
PLLRFCK2 flag
PLLRFCK1 flag
PLLRFCK0 flag
PLLUL flag
Note External circuit
Remarks 1.
2.
3.
4.
PLLMD1 and PLLMD0 (bits 1 and 0 of PLL mode selection register: refer to Figure 17-3) selects
a division mode of the PLL frequency synthesizer.
PLLSCNF (bit 3 of PLL mode selection register: refer to Figure 17-3) selects the least significant
bit of the swallow counter.
PLLRFCK3 through PLLRFCK0 (bits 3 through 0 of PLL reference frequency selection register: refer
to Figure 17-6) selects a reference frequency fr of the PLL frequency synthesizer.
PLLUL (bit 0 of PLL unlock FF register: refer to Figure 17-9) detects the PLL unlock FF status.
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