UPD17704 Datasheet, PDF (264/356 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

µPD17704, 17705, 17707, 17708, 17709
17.4.3 Charge pump
As shown in Figure 17-7, the charge pump outputs the up request and down request signals output by the phase
comparator, from the error out pins (EO1 and EO0 pins).
Therefore, the relationship between the output of the error out pins, divided frequency fN and reference frequency
fr is as follows:
Where reference frequency fr > divided frequency fN: Low-level output
Where reference frequency fr < divided frequency fN: High-level output
Where reference frequency fr = divided frequency fN: Floating
17.4.4 Unlock FF
As shown in Figure 17-7, the unlock FF detects the unlock status of the PLL frequency synthesizer from the up
request and down request signals of the phase comparator.
Because either the up request or down request signal is low in the unlock status, the unlock status is detected by
this low-level signal.
In the unlock status, the unlock FF is set to 1.
The unlock FF is set in the cycle of the reference frequency fr selected at that time. When the contents of the PLL
unlock FF register are read (by the PEEK instruction), the unlock FF is reset (Read & Reset).
Therefore, the unlock FF must be detected in a cycle longer than cycle 1/fr of the reference frequency fr.
The status of the unlock FF is detected by the PLL unlock FF register. Figure 17-9 shows the configuration of the
PLL unlock FF register.
Because this register is a read-only register, its contents can be read to the window register by the “PEEK”
instruction.
Because the unlock FF is set in a cycle of the reference frequency fr, the contents of the PLL unlock FF register
are read to the window register in a cycle longer than cycle 1/fr of the reference frequency.
The delay time of the up and down request signals of the phase comparator are fixed to 0.8 to 1.0 µs.
264