UPD780078 Datasheet, PDF (430/592 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 21 STANDBY FUNCTION
(c) Release by RESET input
When the RESET signal is input, HALT mode is released. And, as in the case with normal reset operation,
the program is executed after branch to the reset vector address.
Figure 21-3. HALT Mode Release by RESET Input
HALT instruction
Wait
(2¹⁷/fX: 15.6 ms)
RESET
signal
Operating
CPU status _mode
Clock
HALT mode
Oscillation
Reset Oscillation stabilization
period wait status
Operating mode
Oscillation
stop
Oscillation
Remarks 1. fX: Main system clock oscillation frequency
2. Values in parentheses are for operation with fX = 8.38 MHz.
Table 21-2. Operation in Response to Interrupt Request in HALT Mode
Release Source
MK××
PR××
IE
Maskable interrupt request
0
0
0
0
0
1
0
1
0
0
1
×
0
1
1
1
×
×
Non-maskable interrupt request
—
—
×
RESET input
—
—
×
ISP
Operation
×
Next address instruction execution
×
Interrupt servicing execution
1
Next address instruction execution
0
1
Interrupt servicing execution
×
HALT mode hold
×
Interrupt servicing execution
×
Reset processing
×: Don’t care
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User’s Manual U14260EJ3V1UD