UPD780078 Datasheet, PDF (294/592 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 15 SERIAL INTERFACE UART2
(d) Reception
The interface enters the reception wait status if the UART transfer mode is specified by using transfer mode
specification register 2 (TRMC2) and bit 5 (RXE2) of asynchronous serial interface mode register 2 (ASIM2)
is set to 1 after bit 7 (POWER2) has been set to 1. In this status, the RXD2 pin is monitored to detect the
start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive
shift register 2 (RX2) at the specified baud rate.
When the stop bit is received, a receive completion interrupt (INTSR2) occurs and, at the same time, the
data in RX2 is written to receive buffer register 2 (RXB2). If an overrun error (OVE2) occurs, however, the
receive data is not written to RXB2 but discarded. Even if a parity error (PE2) or framing error (FE2) occurs
during reception, reception continues up to the position at which the stop bit is received, and an error interrupt
(INTSR2/INTSER2) occurs after completion of reception.
Figure 15-17. Timing of Asynchronous Serial Interface Receive Completion Interrupt Request
RxD2 (input)
Start D0
D1
D2
D6 D7 Parity Stop
INTSR2
RXB2
Caution During reception, the number of stop bits is always 1. A second stop bit is ignored.
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User’s Manual U14260EJ3V1UD