UPD780078 Datasheet, PDF (279/592 Pages) NEC – 8-Bit Single-Chip Microcontrollers

CHAPTER 15 SERIAL INTERFACE UART2
(6) Transfer mode specification register 2 (TRMC2)
This 8-bit register is used to specify the transfer mode, switch the interrupt source of INTST2, enable or disable
occurrence of the receive completion interrupt in the multi-processor transfer mode, and specify the multi-
processor transfer appended bit.
TRMC2 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TRMC2 to 02H.
Figure 15-8. Format of Transfer Mode Specification Register 2 (TRMC2)
Address: FF91H After reset: 02H R/W
Symbol
7
6
5
TRMC2 TRM12^{Note 1} TRM02^{Note 1}
0
4
3
2
1
0
0
ISMD2
0
MPIEN2 MPS2^{Note 2}
TRM12
0
0
1
1
TRM02
0
1
0
1
Transfer mode
UART transfer mode^{Note 3}
Multi-processor transfer mode^{Note 3}
Infrared data transfer (IrDA) mode^{Note 3}
MPIEN2
0^{Notes 6, 7}
1
Receive completion interrupt enable/disable in multi-processor transfer mode^{Note 4}
Condition
INTSR2 enable/disable ^{Note 5}
If “0” is written to this bit
Disabled
• If bit 7 (POWER2) or bit 6 (TXE2) of
asynchronous serial interface mode
register 2 (ASIM2) is cleared to 0
• If bit data has been received with multi-
processor appended bit of “1”
Enabled
ISMD2^{Note 8}
Switching interrupt source of INTST2
0
INTST2 occurs when transmission completed
1
INTST2 occurs when data transfer completed
MPS2
0
1
Setting of multi-processor transmission appended bit^{Note 4}
Appends “0” as and transmits multi-processor appended bit (during data transmission).
Appends “1” as and transmits multi-processor appended bit (during ID transmission).
Notes 1. Before rewriting TRM12 and TRM02, clear bits 6 (TXE2) and 5 (RXE2) of asynchronous serial interface
mode register 2 (ASIM2) to 0.
2. Before setting a value to MPS2, confirm that bit 1 (TXBF) of asynchronous serial interface transmit
status register 2 (ASIF2) is cleared to 0. Before writing transmit data to transmit buffer register 2
(TXB2), specify whether “0” or “1” is appended as the multi-processor appended bit.
3. The setting of bits 0 to 4 (ISEM2, SL2, CL2, PS20, and PS21) of ASIM2 is valid in all the transfer modes.
4. The specification by MPIEN2 and MPS2 is valid only when bit 7 (TRM12) is cleared to 0 and bit 6
(TRM02) is set to 1 (i.e., when the multi-processor transfer mode is set).
User’s Manual U14260EJ3V1UD
279