UPD17717 Datasheet, PDF (354/408 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

µPD17717, 17718, 17719
Table 20-2. Status of Each Pin in Halt and Clock Stop Status and Cautions (2/2)
Pin Function
External interrupt
PLL frequency
synthesizer
Pin Symbol
INT4-INT0
VCOL
VCOH
EO0
EO1
Status of Each Pin and Cautions on Processing
Halt status
Clock stop status
Current consumption increases due to noise if pin is floated
Current consumption increases during PLL PLL is disabled
operation.
When PLL is disabled, pin is in following
status:
VCOH, VCOL : internally pulled down
EO1, EO0 : floated
VCOH, VCOL : internally pulled down
EO1, EO0 : floated
Crystal oscillation
circuit
XIN
XOUT
PLL is automatically disabled if CE pin
goes low
Current consumption changes due to
oscillation waveform of crystal oscillation
circuit.
The higher oscillation amplitude, the lower
current consumption.
Oscillation amplitude must be evaluated
because it is influenced by crystal resonator
or load capacitor used
XIN pin is internally pulled down, and XOUT
pin outputs high level
20.6 Device Operation Control Function of CE Pin
The CE pin controls the following functions by the input level and rising edge of the signal input from an external
source.
• PLL frequency synthesizer
• Interrupt by falling edge of CE pin
• Resetting of device
20.6.1 Controlling operation of PLL frequency synthesizer
The PLL frequency synthesizer can operate only when the CE pin is high.
It is automatically disabled when the CE pin is low.
When the synthesizer is disabled, the VCOH and VCOL pins are internally pulled down, and the EO0 and EO1 pins
are floated. For details, refer to 17.5 PLL Disabled Status.
The PLL frequency synthesizer can be disabled in software even when the CE pin is high.
20.6.2 Controlling interrupt by falling edge input of CE pin
An interrupt can be generated by the falling edge of the CE pin. For details, refer to 12. INTERRUPTS.
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