UPD17717 Datasheet, PDF (262/408 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

µPD17717, 17718, 17719
16.2.11 I²C bus mode operation
The I²C bus mode is provided for when communication operations are performed between a single master
device and multiple slave devices. This mode configures a serial bus that includes only a single master device,
and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the
master device to communicate with a number of (slave) devices using only two lines: SCL and SDA.
Consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and
peripheral devices, using this configuration results in reduction of the required number of port pins and on-board
wires.
In the I²C bus specification, the master sends start condition, data, and stop condition signals to slave devices
through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to
the signal detection function incorporated as hardware. This simplifies I²C bus control sections in the application
program.
An example of a serial bus configuration is shown in Figure 16-39. This system below is composed of CPUs
and peripheral ICs having serial interface hardware that complies with the I²C bus specification.
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because
open-drain buffers are used for the serial clock pin (SCL) and the serial data I/O pin (SDA) on the I²C bus.
The signals used in the I²C bus mode are described in Table 16-9.
Figure 16-39. Example of Serial Bus Configuration Using I²C Bus
Master CPU
VDD VDD
Serial clock
SCL
SDA ^{Serial data bus}
Slave CPU1
SCL
SDA
Slave CPU2
SCL
SDA
Slave IC
SCL
SDA
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