UPD17717 Datasheet, PDF (205/408 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

µPD17717, 17718, 17719
15.4 Duty Setting Block
15.4.1 PWM duty with 8-bit counter selected
The duty setting block compares the value set to each PWM data register (PWMR2 to PWMR0) with the value of
the basic clock counted by each 8-bit counter. If the value of the PWM data register is greater, the block outputs a
high level. If the value of the PWM data register is less, it outputs a low level.
Where the value set to the PWM data register is “x”, therefore, the duty factor can be calculated by the following
expression.
Duty: D = ^{x + 0.25} × 100%
256
Remark 0.25 is an offset, and a high level is output even where x = 0.
Data is set to each PWM data register for each pin via data buffer (DBF). However, the same basic clock, PWM
counter, and output frequency must be selected for each pin. This means that each pin cannot output a duty factor
of a different cycle independently of the others.
Because the basic clock frequency is 1.125 or 0.1125 MHz, the frequency and cycle of the output signal can be
calculated as follows.
(1) Where output frequency is 4.4 kHz and basic clock frequency is 1.125 MHz
1.125 MHz
Frequency: f =
= 4.3945 kHz
256
Cycle:
T=
256
= 227.56 µs
1.125 MHz
(2) Where output frequency is 440 Hz and basic clock frequency is 0.1125 MHz
0.1125 MHz
Frequency: f =
= 439.45 Hz
256
Cycle:
256
T=
= 2.2756 ms
0.1125 MHz
Because the duty setting register of the PWM data registers and timer 3 modulo register are the same register,
they cannot be used at the same time.
When timer 3 is used, PWM data registers 1 and 0 can be used as 8-bit data latches.
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