UPD17016 Datasheet, PDF (223/324 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17016, 17017
19.2 Functional Outline of Serial Interface
The serial interface uses the P0B2/SCK, P0B1/SO, and P0B0/SI pins.
The serial interface can select the internal clock or an external clock, and can execute reception and transfer
operations.
The following subsections 19.2.1 through 19.2.6 outline the functions of the respective blocks of the serial
interface.
For details of each block, refer to 19.3 through 19.7.
19.2.1 Shift clock I/O pin block
This block selects a shift clock I/O pin.
The shift clock I/O pin is selected by the serial I/O mode select register.
Refer to 19.3.
19.2.2 Serial data I/O pin block
This block selects a serial data I/O pin.
The serial data I/O pin is selected by the serial I/O mode select register.
Refer to 19.3.
19.2.3 Clock generation block
This block selects the clock frequency of the shift clock and controls the shift clock output timing.
The shift clock frequency is selected by the serial I/O mode select register.
Refer to 19.4.
19.2.4 Clock counter
The clock counter counts the number of rising edges of the clock output by the shift clock output pin and
outputs a signal at the eighth clock (SF8 signal).
The SF8 signal is used to make serial communication wait (pause).
Refer to 19.5.
19.2.5 Presettable shift register (SIO1SFR)
This shift register sets serial out data and stores serial in data.
It performs a shift operation by using the clock of the shift clock I/O pin and inputs/outputs data.
The output data is set and the input data is read via the data buffer.
Refer to 19.6.
19.2.6 Wait control block
This block controls places or releases serial communication in or from the wait status.
Serial communication is placed in or released from the wait status by the serial I/O mode select register.
Refer to 19.7.
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