N16D1618LPA Datasheet, PDF (8/27 Pages) NanoAmp Solutions, Inc. – 512K × 16 Bits × 2 Banks Low Power Synchronous DRAM

NanoAmp Solutions, Inc.
N16D1618LPA
Advance Information
Figure 6: Mode Register Definition
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
11 10
9
8
7
0
0 WB 0
0
6
5
4
3
CAS Latency
BT
2
1
0
Burst Length
Mode Register (Mx)
M9
Write Burst Mode
0 Burst Read and Burst Write
1 Burst Read and Single Write
M6 M5 M4 CAS Latency
000
Reserved
001
1
010
2
011
3
100
Reserved
101
Reserved
110
Reserved
111
Reserved
M3 Burst Type
0 Sequential
1 Interleave
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
000
1
1
001
2
2
010
4
4
011
8
8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Note: M11(A11) must be sest to “0” to select mode Register (vs. the Extend Mode Register)
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3. The ordering of
accesses within a burst is determined by the burst
length, the burst type and the starting column address,
as shown in Table 3 .
Table 3: Burst Definition
Burst
Length
Starting Column
Address
A2 A1 A0
Order of Access Within a Burst
Sequential
Interleave
2
4
8
Full
Page
0
1
00
01
10
11
000
001
010
011
100
101
110
111
N=A0~7
(Location 0-256)
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
C_n, C_n+1. C_n+2,
C_n+3, C_n+4…
…C_n-1, C_n...
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
Note :
1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the block-of-
two burst; A0 selects the starting column within the
block.
3. For a burst length of four, A2-A7 select the block-of-
four burst; A0-A1 select the starting column within the
block.
4. For a burst length of eight, A3-A7 select the block-of-
eight burst; A0-A2 select the starting column within the
block.
5. For a full-page burst, the full row is selected and A0-
A7 select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Stock No. 23395- Rev L 1/06
8
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.