N16D1618LPA Datasheet, PDF (25/27 Pages) NanoAmp Solutions, Inc. – 512K × 16 Bits × 2 Banks Low Power Synchronous DRAM

NanoAmp Solutions, Inc.
N16D1618LPA
Advance Information
SPECIAL OPERATION FOR LOW POWER CONSUMPTION
TEMPERATURE COMPENSATED SELF REFRESH
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH
mode, according to the case temperature of the Low Power SDRAM device. This allows great power savings during
SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller
have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires
refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher
temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more
often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest
temperature range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh
rate was set to accommodate the higher temperatures. Setting E4 and E3, allow the DRAM to accommodate more
specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF
REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM
is operating at normal temperatures.
PARTIAL ARRAY SELF REFRESH
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of
memory that will be refreshed during SELF REFRESH. The refresh options are Two Bank;all two banks, One
Bank;bank a. WRITE and READ commands can still occur during standard operation, but only the selected banks will
be refreshed during SELF REFRESH. Data in banks that are disabled will be lost.
DEEP POWER DOWN
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole
memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. This mode is
entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the
clock, while CKE is low. This mode is exited by asserting CKE high.
Stock No. 23395- Rev L 1/06
25
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.