N16D1618LPA Datasheet, PDF (24/27 Pages) NanoAmp Solutions, Inc. – 512K × 16 Bits × 2 Banks Low Power Synchronous DRAM

NanoAmp Solutions, Inc.
N16D1618LPA
Advance Information
Table 12: AC CHARACTERISTIC (AC Operating Conditions Unless Otherwise Noted)
PARAMETER
SYM
Refresh Period (4,096 rows)
tREF
AUTO REFRESH period
tRFC
Exit SELF REFRESH to ACTIVE command tXSR
Transition time
tT
-60
MIN MAX
64
66
66
0.5
1.2
-75
MIN MAX
64
67.5
67.5
0.5
1.2
-10
MIN MAX
64
70
70
0.5
1.2
UNIT NOTE
ms
5
ns
5
Note:
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used
to reduce the data rate.
2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge
rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid
data element will meet tOH before going High-Z.
5. Parameter guaranteed by design.
A. Target values listed with alternative values in parentheses.
B. tRFC must be less than or equal to tRC+1CLK
tXSR must be less than or equal to tRC+1CLK
6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate
8. JEDEC and PC100 specify three clocks.
9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.
10. A new command can be given tRC after self refresh exit.
Stock No. 23395- Rev L 1/06
24
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.