N32T1630C1C Datasheet, PDF (12/15 Pages) NanoAmp Solutions, Inc. – 32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM

NanoAmp Solutions, Inc.
N32T1630C1C
Table 1: VAR Update and Deep Sleep Timings
Item
PAR and RMS ZZ low to WE low
Chip (CE, UB/LB) deselect to ZZ low
Deep Sleep Mode
Deep Sleep Recovery
Symbol
t_zzwe
t_cdzz
t_zzmin
t_r
Min Max
1000
0
10
200
Unit
ns
ns
us
us
TABLE 2: Address Patterns for PAR (A3 = 0, A4 = 1)
A2 A1 A0
Active Section
0 1 1 One-quarter of die
0 1 0 One-half of die
1 1 1 One-quarter of die
1 1 0 One-half of die
Address space
Size
000000h - 07FFFFh 512Kb x 16
000000h - 0FFFFFh 1Mb x 16
180000h - 1FFFFFh 512Kb x 16
100000h - 1FFFFFh 1Mb x 16
Density
8Mb
16Mb
8Mb
16Mb
TABLE 3: Address patterns for RMS (A3 = 1, A4 = 1)
A2 A1 A0
Active Section
0 1 1 One-quarter of die
0 1 0 One-half of die
0 0 0 Full die
1 1 1 One-quarter of die
1 1 0 One-half of die
1 0 0 Full die
Address space
Size
000000h - 07FFFFh 512Kb x 16
000000h - 0FFFFFh 1Mb x 16
000000h - 1FFFFFh 2Mb x 16
180000h - 1FFFFFh 512Kb x 16
100000h - 1FFFFFh 1Mb x 16
000000h - 1FFFFFh 2Mb x 16
Density
8Mb
16Mb
32Mb
8Mb
16Mb
32Mb
(DOC# 14-02-005 Rev C ECN 01-0918)
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.