N32T1630C1C Datasheet, PDF (10/15 Pages) NanoAmp Solutions, Inc. – 32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM

NanoAmp Solutions, Inc.
N32T1630C1C
Power Savings Modes
The N32T1630C1C has several power savings modes and the three modes are:
Reduced Memory Size
Partial Array Refresh
Deep Sleep Mode
The operation of the power saving modes is controlled by setting the Variable Address Register (VAR).
This VAR is shown in Figure 8 and is used to enable/disable the various low power modes.
The VAR is set by using the timings defined in figure 9. The register must be set in less then 1us after ZZ is
enabled low.
1) Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and
array size are determined by the settings in the VA register. The VA register is set according to the timings
of Figure 9 and the bit setting of Table 12. The RMS mode is enabled at the time of ZZ transitioning high
and the mode remains active until the register is updated. To return to the full 32Mb address space, the VA
register must be reset using the previously defined procedures.
2) Partial Array Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 8Mb or 16Mb portion of the
array. The mode and array partition to be refreshed are determined by the settings in the VAR register. The
VAR register is set according to the timings of Figure 9 and the bit settings of Table 11. In this mode, when
ZZ is taken low, only the portion of the array that is set in the register is refreshed. The operating mode is
only available during standby time and once ZZ is returned high, the device resumes full array refresh. All
future PAR cycles will use the contents of the VA register. To change the address space of the PAR mode,
the VA register must be reset using the previously defined procedures.
There are two different device versions that have different default settings for the PAR mode.
In the first version, the default state for the ZZ enable/disable register will be ZZ enabled where ZZ low will
initiate a deep sleep mode after 1us. This device is referred to as Deep Sleep Active, or DSA device. In the
second version, the default state for the ZZ register will be such that ZZ low will put the device into PAR
mode after 1us and never initiate a deep sleep mode unless appropriate register is updated. This device is
referred to as Deep Sleep Inactive, or DSI device. In either device, once the SRAM enters Deep Sleep
Mode, the VAR contents are destroyed and the default register settings are reset.
3) Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep
Sleep is entered by bringing ZZ low. After 1 us, if the VAR register corresponding to A4 is not set to Deep
Sleep Disabled, the device will enter Deep Sleep Mode. The device will remain in this mode as long as ZZ
remains low.
(DOC# 14-02-005 Rev C ECN 01-0918)
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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.