N32T1630C1C Datasheet, PDF (11/15 Pages) NanoAmp Solutions, Inc. – 32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM

NanoAmp Solutions, Inc.
FIGURE 2: Variable Address Register
N32T1630C1C
A20 - A5
A4
A3
A2
A1
A0
Array mode for ZZ
Reserved for future
Preferably set to all 0
0 = PAR mode (default)
1
1 = RMS mode
1
0
ZZ Enable/Disable
0
0 = Deep Sleep Enabled
(default for DSA device)
1 = Deep Sleep Disabled
(default for DSI device)
Array half
0 = Bottom array (default)
1 = Top array
Array section
1 = 1/4 array
0 = 1/2 array
1 = Reserved
0 = Full array
(default)
FIGURE 3: Variable Address Register (VAR) Update Timings
A0-A4
CE
WE
t_CDZZ
ZZ
LB, UB
t_AS
t_ZZWE
t_WC
t_AW
t_WR
t_WP
t_{LBW, UBW}
FIGURE 4: Deep Sleep Mode - Entry/Exit Timings
t_ZZMIN
ZZ
t_CDZZ
t_R
CE or
LB, UB
(DOC# 14-02-005 Rev C ECN 01-0918)
11
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.