ADS-230 Datasheet, PDF (6/12 Pages) Murata Power Solutions Inc. – Low-Power, 12-Bit, 1.0/1.5MHz Sampling A/D Converter

ADS-230/ADS-231
®
®
4.096V
+5V
1kΩ
VT = 4.096V
LM4040–4.1
1~0µA
0.01µF
1=5.9mA
7.02V
1kΩ
VTS
500Ω
VT
10µF 0.1µF
RS
SENSE LINE
4.096V
FORCE LINE
Rf
VR = VT – VB = 4.096V
Rf = 0.5Ω (FORCE LINE IMPEDANCE)
RS = 10Ω (SENSE LINE IMPEDANCE)
RLADDER = 750Ω
0.1µF
VR/16
REFERENCE
LADDER
ADS-230/231
VB = 0.000V
0.000V
–2.93V
–0.003V
1 = 5.9mA 500Ω
VB
Rf
0.01µF
10µF
1kΩ
0.1µF
1~0µA
VBS
RS
Figure 4. Ladder Reference Force and Sense Inputs
FORCE LINE
0.000V
SENSE LINE
Reference Inputs
Reference voltages are applied to the fully differential VT
and VB reference input pins. The resistance of the refer-
ence ladder network is typically 750 ohms. Additional
parasitic resistances are added by the package leads, wire
bonds, conductor traces, etc. These parasitic resistances
can introduce voltage drops causing gain and offset errors
as large as 6 LSB's at the 12-bit level. These IR drops can
be compensated for by sensing the reference voltages at
the VTS and VBS reference sense pins and forcing the
reference voltage an exact value as shown in Figure 4.
Since there is essentially zero current flowing through the
sense line there is negligible voltage drop to the inverting
input of the op-amp. The voltage at the inverting input of
the op-amp, therefore, accurately represents the voltage at
the top or bottom of the reference ladder network. The op-
amp drives the force input and forces the voltages at the
ends of the reference ladder network to equal the voltage
at the op-amps non-inverting input, plus or minus the op-
amps input offset voltage. When using this reference
configuration with a low offset voltage op-amp, gain and
offset errors below 0.5 LSB are readily obtainable.
The 0.1 and 10µF capacitors on the force inputs provide
high frequency decoupling of the reference ladder network.
The 500Ω force resistors isolate the op-amp from the large
capacitive load. The 0.01µF and 1kΩ network ensures
stability at high frequencies. The VR/16 output should be
bypassed to analog ground with a 0.1µF ceramic capacitor.
All bypass capacitors should be located as close to the
pins as possible to minimize noise on the reference ladder.
If the ADS-230/-231 is used in a frequency domain
application then the circuit shown in Figure 3 maybe used.
This circuit will introduce several LSB's of gain and offset
error, but the dynamic performance will be unaffected.
The reference inputs are fully differential and define the full-
scale range of the input signal. The maximum range can be
up to 5 volts, or when required any span within the 0 to 5V
limit may be used. When using lower voltage spans the
noise performance will degrade. See the Typical
Performance Curves.
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