ADS-230 Datasheet, PDF (4/12 Pages) Murata Power Solutions Inc. – Low-Power, 12-Bit, 1.0/1.5MHz Sampling A/D Converter

ADS-230/ADS-231
®
®
AVS, DVS
AGND, DGNDC, DGNDD
BIT 1 – BIT 12
CH1IN, CH2IN
MUX OUT
ANALOG INPUT
SEL
MD
TEST
CS
INT
EOC
RD
OE
S/H
PD
VR/16
VT, VB
VTS, VBS
PIN DESCRIPTIONS
These are the analog and digital power supply input pins. They should all be connected to
the same voltage source. Both AVS pins should be bypassed to AGND and the DVS pin to
DGNDD. Bypass using a 0.1µF ceramic capacitor in parallel with a 10µF tantalum
capacitor.
These are the analog and digital ground pins. All of the ground pins should be returned to
the same potential and connected to a stable, noise-free system ground. AGND is the
analog ground. DGNDC is the ground for the digital control lines. DGNDD is the digital
ground for the output data bus.
These are the three-state data output pins. Output is enabled by RD, CS, and OE.
These are the analog input pins to the internal input multiplexer.
This is the output of the internal multiplexer,
This is the direct input to the sampling A to D converter.
This is the multiplexer channel select pin. The input is selected based on the state of SEL
when EOC transitions low. A low selects channel one and a high selects channel two. See
Table 1.
Connect to DGNDC
Connect to DVS.
This is the Chip Select control input. When low, this pin enables the RD, S/H and OE inputs.
This pin can be tied low.
This is the Interrupt output pin. When using the Interrupt Interface Mode, this output goes
low when a conversion is completed and indicates that the data is available in the output
latches. This output is always high when RD is held low. Refer to the Timing Diagrams.
This is the End of Conversion output pin. EOC is low during a conversion.
This is the Read control input pin. When RD and CS are low, the INT output is reset and, if
EOC is high, data appears on the data bus. This pin can be tied low.
This is the Output Enable control input pin. The data output pins are in the high impedance
state when OE is low. Data appears when OE is high and CS and RD are both low. This pin
can be tied high.
This is the Sample and Hold control input pin. When CS is low a new conversion is initiated
by the falling edge of this input.
This is the Power Down control input pin. This pin is held high for normal operation. When
the input is low, the A to D converter goes into power standby mode.
Bypass this pin to AGND using a 0.1µF ceramic capacitor.
These are the positive (top) and negative (bottom) voltage reference force input pins,
respectively.
These are the positive (top) and negative (bottom) voltage reference sense pins,
respectively.
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