ADS-230 Datasheet, PDF (5/12 Pages) Murata Power Solutions Inc. – Low-Power, 12-Bit, 1.0/1.5MHz Sampling A/D Converter

®
®
ADS-230/ADS-231
TECHNICAL NOTES
The Analog Input
For maximum performance, the source impedance driving the
input of the ADS-230/-231 should be as low as possible. A
source impedance of less than 100 ohms is recommended.
See the Typical Performance Curves.
If the signal source has high output impedance, the output
should be buffered with an op-amp capable of driving a
switched 25pF/100ohm load. Any ringing or instability of the
op-amp during the sampling period can cause conversion
errors.
Using a high-speed buffer also improves the THD
performance when using the internal MUX. The MUX on-
resistance is non-linear over the range of the input voltage;
this causes the RC time constant of the equivalent circuit
shown in Figure 2 to vary with input voltage. This results in
harmonic distortion with increasing frequency. Inserting a
buffer between the MUX OUT and ANALOG INPUT terminals
will eliminate the loading on RMUX and significantly reduce
THD.
The analog input of the ADS-230/-231 can be modeled as
shown in Figure 2. The S/H switch is closed during the sample
period, and open during hold. The hold capacitor (CH) has to
be charged to the input voltage by the source within the
sample period. The source impedance (RS) will directly effect
the charge time. If RS is too large, the voltage across CH will
not settle to within ½ LSB's of the source voltage before
conversion begins. This will result in conversion errors.
The combination of RS, RMUX, RSW and CH form a low-pass
filter. Therefore, minimizing RS will increase the frequency
response of the converter.
The settling time to n bits is:
tSETTLE = (RS + RMUX + RSW) * CH * n * In(2)
The bandwidth of the input circuit is:
F (–3dB) = 1/[2 * 3.14 * (RS + RMUX + RSW) * CH]
Internal Multiplexer
Both the ADS-230 and ADS-231 have an internal multiplexer
that is controlled by the logic level on the SEL pin when EOC
goes low. See the timing diagrams. The MUX setup and hold
times can be determined from the following:
tMS(wrt S/H) = tMS –tEOC (min)
tMS(wrt S/H) = 50–60
tMS(wrt S/H) = –10ns
tMH(wrt S/H) = tMH + tEOC (max)
tMH(wrt S/H) = 50 +125
tMH(wrt S/H) = 175ns
Note that the –10ns indicates that data on SEL must be valid
within 10ns of the S/H pulse going low in order to meet the
setup time requirements. SEL must be valid for the length of
time determined by the following equation:
(tMS + tEOC(max)) – (tMS – tEOC (min)) = 185ns
Table 1 shows the coding for MUX channel selection.
The output of the MUX is available at the MUX OUT pin. This
output allows the user to perform additional signal processing,
such as buffering, filtering or gain, before the signal is brought
to the ANALOG INPUT pin. If signal processing is not required
connect the MUX OUT pin directly to the ANALOG INPUT pin.
Table 1. Internal Multiplexer Programming
SEL
Channel
0
CH1IN
1
CH2IN
CH1IN
RS
CH2IN
MUX OUT
VSOURCE
ANALOG
INPUT
TYPICAL VALUES
RMUX = 100
RSW = 100
CH = 25pF
ADS-230/231
RMUX
RSW
S/H
SWITCH
TO COMPARATORS
CH
Figure 2. ADS-230/-231 Input Stage Model
+5V ±5%
60Ω
VTS NC
4.096V
VT
10µF 0.1µF
4.093V
0.1µF
VR/16
REFERENCE
LADDER
ADS-230/231
VB
VBS NC
0.003V
Figure 3. Reference Force Input Only
5