DSP56362 Datasheet, PDF (97/168 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor

Freescale Semiconductor, Inc.
Specifications
Serial Host Interface SPI Protocol Timing
Table 2-21 Serial Host Interface SPI Protocol Timing (Continued)
No. Characteristics
Mode
Filter
Mode
Expression
100MHz
Unit
Min Max
Bypassed 0.5×t_SPICC –10 43 —
Master Narrow 0.5×t_SPICC –10 96 —
142 _{Serial clock high period}
Slave
Wide
Bypassed
Narrow
0.5×t_SPICC –10
2.5×T_C+12
2.5×T_C+102
131
37
127
—
—
—
ns
Wide
2.5×T_C+189 214 —
Bypassed 0.5×t_SPICC –10 43 —
Master Narrow 0.5×t_SPICC –10 96 —
143 _{Serial clock low period}
Slave
Wide
Bypassed
Narrow
0.5×t_SPICC –10
2.5×T_C+12
2.5×T_C+102
131
37
127
—
—
—
ns
Wide
2.5×T_C+189 214 —
144
Serial
time
clock
rise/fall
Master
Slave
—
—
—
—
—
—
10
2000
ns
SS assertion to first
SCK edge CPHA = 0
146
Slave
Bypassed
Narrow
Wide
Bypassed
3.5×T_C+15
0
0
10
50 —
0
—
0
10
—
—
ns
CPHA = 1
Slave Narrow
0
0
—
Wide
0
0
—
Bypassed
12
147
Last SCK edge to SS
not asserted
slave
Narrow
Wide
102
189
12 —
102 — ns
189 —
Data input valid to SCK ^{Master Bypassed}
0
0
—
148 _{edge (data input set-up} /Slave Narrow MAX{(20-T_C), 0} 10 — ns
time)
Wide MAX{(40-T_C), 0} 30 —
SCK last sampling
149 _{edge to data input not}
valid
Bypassed
Master
/Slave
Narrow
Wide
2.5×T_C+10
2.5×T_C+30
2.5×T_C+50
35 —
55 — ns
75 —
150
SS assertion
out active
to data
Slave
—
2
2
— ns
151
SS deassertion to data
high impedance
Slave
—
SCK edge to data out
152 _{valid (data out delay}
time)
Bypassed
Master
/Slave
Narrow
Wide
9
2×T_C+33
2×T_C+123
2×T_C+210
—
9 ns
— 53
— 143 ns
— 230
MOTOROLA
DSP56362 Advance Information
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