DSP56362 Datasheet, PDF (108/168 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor

Specifications
Freescale Semiconductor, Inc.
Enhanced Serial Audio Interface Timing
Table 2-24 Enhanced Serial Audio Interface Timing (Continued)
100 MHz
No.
Characteristics^{1, 2, 3}
Symbol Expression
Min Max
Cond-ition⁴
Unit
445
Flags input hold time after RXC
falling edge
—
—
6.0 —
0.0 —
x ck
i ck s
ns
446
TXC rising edge to FST out (bl)
high
—
—
— 29.0
x ck
— 15.0
i ck
ns
447 _{TXC rising edge to FST out (bl) low} —
—
— 31.0
x ck
— 17.0
i ck
ns
448
TXC rising
high⁶
edge
to FST out (wr)
—
—
— 31.0
x ck
— 17.0
i ck
ns
449
TXC
low⁶
rising
edge
to FST out (wr)
—
—
— 33.0
x ck
— 19.0
i ck
ns
450
TXC rising edge to FST out (wl)
high
—
—
— 30.0
x ck
— 16.0
i ck
ns
451 _{TXC rising edge to FST out (wl) low} —
—
— 31.0
x ck
— 17.0
i ck
ns
452
TXC rising edge to data out enable
from high impedance
—
—
— 31.0
x ck
— 17.0
i ck
ns
453
TXC rising edge to transmitter drive
enable assertion
—
—
— 34.0
x ck
— 20.0
i ck
ns
454 _{TXC rising edge to data out valid}
—
23 + 0.5 × T_C ^{— 28.0}
21.0
— 21.0
x ck
i ck
ns
455
TXC rising edge
impedance⁷
to data out high
—
—
— 31.0
x ck
— 16.0
i ck
ns
456
TXC rising edge to transmitter drive
enable deassertion⁷
—
—
— 34.0
x ck
— 20.0
i ck
ns
457
FST input (bl, wr) setup time before
TXC falling edge⁶
—
—
2.0 —
21.0 —
x ck
i ck
ns
458
FST input (wl) to data out enable
from high impedance
—
—
— 27.0
—
ns
459
FST input (wl) to transmitter drive
enable assertion
—
460
FST input (wl) setup time before
TXC falling edge
—
461
FST input hold time after TXC
falling edge
—
462
Flag output valid after TXC rising
edge
—
—
— 31.0
—
ns
—
2.0 —
21.0 —
x ck
i ck
ns
—
4.0 ——
x ck
0.0 —
i ck
ns
—
— 32.0
x ck
— 18.0
i ck
ns
463 _{HCKR/HCKT clock cycle}
—
—
40.0 —
ns
2-70
DSP56362 Advance Information
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