DSP56362 Datasheet, PDF (61/168 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor

Freescale Semiconductor, Inc.
Specifications
External Memory Expansion Port (Port A)
Table 2-9 DRAM Page Mode Timings, One Wait State
(Low-Power Applications)^{1, 2, 3}
No.
Characteristics
Symbol Expression
20 MHz⁶
30 MHz⁶
Unit
Min Max Min Max
Page mode cycle time for
two consecutive accesses of
131 ^{the same direction}
t_PC
Page mode cycle time for
mixed (read and write)
accesses.
2 × T_C
1.25 x Tc
100.0 — 66.7 —
ns
62.5 — 41.7 —
132
CAS assertion to data valid
(read)
t_CAC
T_C − 7.5
— 42.5 — 25.8 ns
133
Column address valid to
data valid (read)
t_AA
1.5 × T_C − 7.5 — 67.5 — 42.5 ns
134
CAS deassertion to data not
valid (read hold time)
t_OFF
0.0 — 0.0 — ns
135
Last CAS assertion to RAS
deassertion
t_RSH 0.75 × T_C − 4.0 33.5 — 21.0 — ns
136
Previous CAS deassertion to
RAS deassertion
t_RHCP
2 × T_C − 4.0 96.0
—
62.7
—
ns
137 _{CAS assertion pulse width}
t_CAS 0.75 × T_C − 4.0 33.5 — 21.0 — ns
Last CAS deassertion to
RAS deassertion⁴
138
•
•
BRW[1:0] = 00
BRW[1:0] = 01
• BRW[1:0] = 10
• BRW[1:0] = 11
t_CRP
1.75 × T_C − 6.0 81.5
3.25 × T_C − 6.0 156.5
—
—
52.3
102.2
—
—
ns
4.25 × T_C − 6.0 206.5 — 135.5 —
6.25 × T_C – 6.0 306.5 — 202.1 —
139 _{CAS deassertion pulse width} t_CP 0.5 × T_C − 4.0 21.0 — 12.7 — ns
140
Column address valid to
CAS assertion
t_ASC 0.5 × T_C − 4.0 21.0 — 12.7 — ns
141
CAS assertion to column
address not valid
t_CAH 0.75 × T_C − 4.0 33.5 — 21.0 — ns
142
Last column address valid to
RAS deassertion
t_RAL
2 × T_C − 4.0 96.0 — 62.7 — ns
143
WR deassertion to CAS
assertion
t_RCS 0.75 × T_C − 3.8 33.7 — 21.2 — ns
144
CAS deassertion to WR
assertion
t_RCH 0.25 × T_C − 3.7 8.8
—
4.6
— ns
145
CAS assertion to WR
deassertion
t_WCH 0.5 × T_C − 4.2 20.8 — 12.5 — ns
MOTOROLA
DSP56362 Advance Information
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