DSP56362 Datasheet, PDF (58/168 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor

Specifications
Freescale Semiconductor, Inc.
External Memory Expansion Port (Port A)
Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz³ (Continued)
No. Characteristics Symbol
Expression¹
100 MHz 120 MHz
Unit
Min Max Min Max
113
RD deassertion
time
100 MHz
0.75 × T_C − 4.0
[1 ≤ WS ≤ 3]
1.75 × T_C − 4.0
[4 ≤ WS ≤ 7]
3.5 — 2.2 —
13.5 — 10.6 — ^ns
2.75 × T_C − 4.0
[WS ≥ 8]
23.5 — 18.9 —
100 MHz
0.5 × T_C − 4.0
[WS = 1]
1.0 — 0.2 —
114
WR deassertion
time
T_C − 2.0
[2 ≤ WS ≤ 3]
2.5 × T_C − 4.0
[4 ≤ WS ≤ 7]
6.0 — 6.3 —
ns
21.0 — 16.8 —
3.5 × T_C − 4.0
[WS ≥ 8]
31.0 — 25.2 —
115
Address valid to
RD assertion
116
RD assertion pulse
width
117
RD deassertion to
address not valid
100 MHz
0.5 × T_C − 4.0
100 MHz
(WS + 0.25) × T_C −4.0
100 MHz
0.25 × T_C − 2.0
[1 ≤ WS ≤ 3]
1.25 × T_C − 2.0
[4 ≤ WS ≤ 7]
1.0 — 0.2 — ns
8.5 — 6.4 — ns
0.5 — 0.1 —
10.5 — 8.4 — ^ns
2.25 × T_C − 2.0
[WS ≥ 8]
20.5 — 16.7 —
TA setup before
118 _{RD or WR}
deassertion⁴
0.25 × T_C + 2.0
4.5 — 4.1 — ns
119
TA hold after RD or
WR deassertion
0 — 0.0 — ns
Notes: 1. WS is the number of wait states specified in the BCR.
2. Timings 100, 107 are guaranteed by design, not tested.
3. All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc
4. In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to
remain active
5. Timing 110, 111, and 112, are not specified for 100 MHz.
2-20
DSP56362 Advance Information
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