MC145474 Datasheet, PDF (92/111 Pages) Motorola, Inc – ISDN S/T Interface Transceiver

M receive FIFOs from the IDL M timeslot position). A further condition can be placed on the data
prior to its being loaded into the IDL receive FIFOs. This condition is called the HOZ condition. The
HOZ condition is enabled for the IDL A receive FIFOs by setting BR8(4) to a ‘1’. Correspondingly,
the HOZ condition is enabled for the IDL M receive FIFOs by setting BR8(5).
When the HOZ condition is disabled data will be loaded into the IDL receive FIFOs on eight bit
boundaries after the setting of the activate IDL FIFO bit to ‘1’. When the HOZ condition is enabled
(the HOZ condition is enabled by setting the HOZ bit to ‘1’) data received via the IDL A and IDL M
timeslots will be internally monitored by the device. (Note that the activate IDL FIFO bit must be set
to ‘1’ after the HOZ bit has been set to ‘1’). Data received in the IDL A and IDL M timeslots will be
ignored until the first ‘0’ is received. Upon reception of the first ‘0’, data will subsequently be loaded
into the receive FIFOs (data received in the IDL A timeslot gets loaded into the IDL A receive FIFOs,
data received in the IDL M timeslot gets loaded into the IDL M receive FIFOs) on eight bit
boundaries, until the FIFOs are filled. Note that the first ‘0’ received will be the MSB of the first byte
loaded into the receive FIFOs. Note also that after the first ‘0’ has been received the HOZ bit will
be internally reset to ‘0’. For correct use of the HOZ flow control one should first set the HOZ bit to
‘1’ and then set the activate IDL FIFO bit to ‘1’.
After reading a byte from the FIFOs, the data is upshifted. If the IDL receive FIFO is not read after
being filled up, then the last byte will be overwritten. This corresponds to FIFO location #1 as shown
in Figure 12-2. When the FIFOs have been completely emptied then the whole process can be
repeated i.e., set the activate and/or set the HOZ. Note that the HOZ flow control is optional, but
if this control is being used it should be set to ‘1’ prior to the activate IDL FIFO bit being set to ‘1’.
SCP BYTE REGISTER
ENABLE IRQ #4
ENABLE IRQ #5
IRQ #4
IRQ #5
IDL Rx
ACTIVATE IDL FIFO
RECEIVE
FIFOS
IDL RECEIVE
FIFO ≤ 1/2 FULL
MOTOROLA
12-4
NOTES:
1. HOZ set. Data gets loaded into FIFOs after first ‘0’ received.
2. HOZ not set. Data gets loaded into FIFO immediately.
Figure 12-3. Flow Control for Receive FIFOs
MC145474 • MC145475