MC145474 Datasheet, PDF (48/111 Pages) Motorola, Inc – ISDN S/T Interface Transceiver

6.11 IDL SYNC
This pin is part of the IDL. The IDL SYNC pin is bi-directional. When the MC145474/75 is operating
as an IDL slave, this pin is an input to the device. Conversely, when the device is operating as an
IDL master, this pin is an output. The MC145474/75 configured as an NT comes out of reset as an
IDL slave. The NT configured device can be programmed to act as an IDL master by setting BR7(3).
The MC145474/75 acting as a TE is always an IDL master. IDL SYNC is a single positive polarity
pulse, one full IDL CLK cycle in duration. IDL SYNC occurs in the bit period immediately preceding
the IDL data transaction.
The IDL SYNC signal is to be periodic at 125 µs intervals. The IDL SYNC input in combination with
the IDL CLK input conveys the networks timing information to the NT IDL slave device. Data is
shifted into the MC145474/75 via IDL Rx on the first 20 falling edges of IDL CLK after the falling edge
of IDL CLK which occurred during the high period of IDL SYNC. Data is shifted out of the device
on the first 20 rising edges of IDL CLK after falling edge of IDL CLK which occurred during the high
period of IDL SYNC.
In the TE configured MC145474/75, IDL SYNC is leading edge aligned with IDL CLK, is one IDL
CLK period in duration and is periodic at a 125 µs rate. The position of the TEs IDL SYNC relative
to the TEs transmitted INFO 3 is phase locked to the incoming transmission from the NT, when the
TE device is receiving either INFO 2 or INFO 4. When the TE device has no timing information from
the NT (i.e., it has not recognized either INFO 2 or INFO 4) it’s IDL SYNC output has the option of
free running or to be held low, as programmed by the IDL FREE RUN bit in the SCP (BR7(3)).
6.12 IDL CLK
This pin is part of the IDL. The IDL CLK pin is bi-directional. When the MC145474/75 is operating
as an IDL slave, this pin is an input to the device. Conversely, when the device is operating as an
IDL master, this pin is an output. The MC145474/75 configured as an NT comes out of reset as an
IDL slave. The NT configured device can be programmed to act as an IDL master by setting BR7(3).
The MC145474/75 acting as a TE is always an IDL master. IDL CLK is used for the input and output
of digital data. Twenty bits of data are input simultaneous with the output of 20 bits via the IDL Rx
and IDL Tx pins, respectively. The data transfers take place on the 20 IDL CLK cycles immediately
following the IDL SYNC pulse. Data is clocked into the MC145474/75 via the IDL Rx pin on the first
20 falling edges of IDL CLK following IDL SYNC. Data is shifted out of the device on the first 20 rising
edges of IDL CLK following IDL SYNC.
When the MC145474/75 S/T transceiver is operating as an NT IDL slave it can accept any of the
following frequencies for IDL CLK: 1.536,1.544, 2.048, 2.56 or 4.096 MHz. IDL SYNC should be
8 kHz and be one IDL CLK cycle in duration. When the MC145474/75 S/T transceiver is operating
as an NT IDL master it will output IDL CLK at one of the following frequencies: 1.536, 2.048 or 2.56
MHz. The IDL CLK rate is determined by the setting of BR7(2) AND BR13(5). IDL SYNC will be one
IDL CLK period in duration and will be at an 8 kHz rate. When the MC145474/75 S/T transceiver
is operating as a TE IDL master it will output IDL CLK at one of the following frequencies: 2.048 or
2.56 MHz. The IDL CLK rate is determined by BR7(2). IDL SYNC will be one IDL CLK period in
duration and will be at an 8 kHz rate.
6.13 IDL Rx
This pin is part of the IDL and is always an input to the MC145474/75 S/T transceiver. Data is read
into the MC145474/75 from the IDL bus via the IDL Rx pin. Data is read into the device on the first
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MC145474 • MC145475