MC145474 Datasheet, PDF (85/111 Pages) Motorola, Inc – ISDN S/T Interface Transceiver

10.6 WRITING Q CHANNEL DATA TO A TE CONFIGURED MC145474/75
Data written to BR2(7:4) is transmitted in the Q channel. The TE configured MC145474/75 polls this
internal register once every 5 ms (a multiframe is 5 ms in duration). If no new data has been written
to this register, the old data is re-transmitted. When multiframing is disabled, the data in this register
is ignored and the Fa bit obeys the multiframing wrapping criteria as outlined in CCITT I.430 and
ANSI T1.605.
BR2(7:4) comes out of reset in the all ones state in the TE mode of operation. To accommodate
other TEs on the loop, BR2(7:4) should be left in the all ones state when the TE does not have
access to the Q channel.
10.7 MULTIFRAME INTERRUPTS IN A TE CONFIGURED MC145474/75
The TE will generate an interrupt either once every multiframe or only in the event of a new SC1
subchannel nibble having been received. A new SC1 subchannel nibble is defined as one which
differs from the previous SC1 nibble. Table 10-3 illustrates how to configure a TE for either of these
options.
Table 10-3. TE Multiframe Interrupts
BR3(2)
Interrupt Every
Multiframe
X
0
1
NR4(2)
Enable Multiframing
Interrupt
0
1
1
IRQ
MC145474 (Pin 16)
MC145475 (Pin 20)
Multiframing never causes an interrupt
An interrupt is generated on the reception of
a new SC1 subchannel nibble
An interrupt is generated every multiframe
10.8 READING S SUBCHANNEL DATA FROM A TE CONFIGURED MC145474/75
The S subchannel nibbles SC1, SC2, SC3, SC4, and SC5 received from the NT, are obtained by
reading BR3(7:4), BR9(7:4), BR9(3:0), BR10(7:4), and BR10(3:0), respectively. The demodulated
S subchannel data is written to these registers every 5 ms. These registers are read only registers
in the TE mode of operation.
10.9 FAR END CODE VIOLATION (FECV) DETECTION
A Far-End Code Violation (FECV) occurs when a multiframe incoming to the NT from the TE(s)
contains one or more illegal S/T line code violations. An FECV maintenance message, as defined
in ANSI T1.605, indicates to the TEs that an FECV has occurred. This message is transmitted from
the NT to the TEs through the SC1 subchannel. In an NT configured MC145474/75 the ‘‘FECV
Detection’’ interrupt (IRQ #6) will indicate that an FECV has occurred. The FECV interrupt status
bit is located in NR3(1) and its corresponding enable bit is located in NR4(1).
MC145474 • MC145475
MOTOROLA
10-3