MC145474 Datasheet, PDF (56/111 Pages) Motorola, Inc – ISDN S/T Interface Transceiver

7.2.4 NR0(0) — Return to Normal
When this bit is ‘0’, the MC145474/75 functions normally. When this bit is ‘1’, the following bits are
reset:
BR11(0)
BR11(1)
BR6(7:0)
98 kHz test tone
External analog loopback
Note that NR0(0) is a read/write bit.
7.3 NIBBLE REGISTER 1
This register is a read only register and can be reset by application of either a hardware or software
reset. A per bit description of nibble register 1, ‘‘NR1’’ is as follows.
7.3.1 NR1(3) — Activation Indication (AI)
This bit is set by the MC145474/75 when the loop is fully activated. Thus if the chip is configured
as an NT, this bit is set when it is transmitting INFO 4 and receiving INFO 3. Conversely, if the chip
is configured as a TE, this bit is set when it is transmitting INFO 3 and receiving INFO 4. Note that
NR1(3) is a read only bit.
7.3.2 NR1(2) — Error Indication (EI)
NR1(2) is set by the MC145474/75 S/T transceiver to indicate an error condition has been detected
by the activation state machine of the transceiver, as outlined in CCITT I.430 and ANSI T1.605. The
low to high level transition of the EI bit corresponds to the EI1 error indication reporting, while the
high to low level transition of the EI bit corresponds to the EI2 error indication reporting recovery.
Note that NR1(2) is a read only bit.
7.3.3 NR1(1) — TE: Multiframing Detection (MD)
NT: Not Applicable
In the TE mode of operation this bit is set by the MC145474/75 S/T transceiver whenever it detects
multiframing from the NT. This bit will be set low if multiframing synchronization is lost and will return
high when synchronization is re-acquired. This bit applies only to TE configured devices. Note that
NR1(1) is a read only bit.
7.3.4 NR1(0) — Frame Sync (FS)
NR1(0) is set high by the MC145474/75 S/T transceiver when frame synchronization is achieved.
NR1(0) is reset by the MC145474/75 whenever frame synchronization is lost. Note that NR1(0) is
a read only bit.
7.4 NIBBLE REGISTER 2
This register is a read/write register and can be cleared by application of either a hardware or
software reset. A per bit description of nibble register 2, ‘‘NR2’’ is as follows.
MOTOROLA
7-2
MC145474 • MC145475