56F803 Datasheet, PDF (9/48 Pages) Motorola, Inc – 56F803 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
Address, Data, and Bus Control Signals
No. of
Pins
1
Signal
Name
CLKO
Table 6. PLL and Clock (Continued)
Signal State During
Type
Reset
Signal Description
Output
Chip-driven
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 7. Address Bus Signals
No. of
Pins
Signal
Name
Signal State During
Type
Reset
Signal Description
6
A0–A5 Output
Tri-stated
Address Bus—A0–A5 specify the address for external Program
or Data memory accesses.
2
A6–A7 Output
Tri-stated
Address Bus—A6–A7 specify the address for external Program
or Data memory accesses.
GPIOE2– Input/
GPIOE3 Output
Input
Port E GPIO—These two pins are General Purpose I/O (GPIO)
pins that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15 Output
Tri-stated
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
GPIOA0– Input/
GPIOA7 Output
Input
Port A GPIO—These eight pins are General Purpose I/O (GPIO)
pins that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
No. of
Pins
16
Signal
Name
D0–D15
Table 8. Data Bus Signals
Signal State During
Type
Reset
Signal Description
Input/
Output
Tri-stated
Data Bus— D0–D15 specify the data for external Program or
Data memory accesses. D0–D15 are tri-stated when the
external bus is inactive. Internal pull-ups may be active.
56F803 Technical Data
9
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