56F803 Datasheet, PDF (14/48 Pages) Motorola, Inc – 56F803 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
2.11 Analog-to-Digital Converter (ADC) Signals
Table 16. Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal State During
Type
Reset
Signal Description
4
ANA0–3 Input
4
ANA4–7 Input
1
VREF
Input
Input
Input
Input
ANA0–3—Analog inputs to ADC channel 1
ANA4–7—Analog inputs to ADC channel 2
VREF—Analog reference voltage for ADC. Must be set to
V_DDA-0.3V for optimal performance.
2.12 Quad Timer Module Signals
Table 17. Quad Timer Module Signals
No. of Pins
Signal Name
Signal Type State During Reset
Signal Description
2
TD1–2
Input/Output
Input
TD1–2— Timer D Channel 1–2
2.13 JTAG/OnCE
Table 18. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
1
1
1
1
1
1
Signal
Name
TCK
TMS
TDI
TDO
TRST
DE
Signal
Type
State During
Reset
Signal Description
Input Input, pulled low Test Clock Input—This input pin provides a gated clock to
(Schmitt) internally synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
Input
(Schmitt)
Input, pulled
high internally
Test Mode Select Input—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Input
(Schmitt)
Input, pulled
high internally
Test Data Input—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
Output
Tri-stated
Test Data Output—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
Input
(Schmitt)
Input, pulled
high internally
Test Reset—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted at power-up and whenever
RESET is asserted. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
Output
Output
Debug Event—DE provides a low pulse on recognized debug
events.
14
56F803 Technical Data
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