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56F803 Datasheet, PDF (38/48 Pages) Motorola, Inc – 56F803 16-bit Hybrid Controller | |||
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Freescale Semiconductor, Inc.
3.14 JTAG Timing
Table 36. JTAG Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0â3.6 V, TA = â40° to +85°C, CL ⤠50pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation2
fOP
DC
10
MHz
TCK cycle time
tCY
100
â
ns
TCK clock pulse width
tPW
50
â
ns
TMS, TDI data set-up time
tDS
0.4
â
ns
TMS, TDI data hold time
tDH
1.2
â
ns
TCK low to TDO data valid
tDV
â
26.6
ns
TCK low to TDO tri-state
tTS
â
23.5
ns
TRST assertion time
tTRST
50
â
ns
DE assertion time
tDE
4T
â
ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
VIH
TCK
(Input)
VM = VIL + (VIH â VIL)/2
tCY
tPW
VM
VIL
tPW
VM
Figure 30. Test Clock Input Timing Diagram
38
56F803 Technical Data
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Go to: www.freescale.com
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