56F803 Datasheet, PDF (1/48 Pages) Motorola, Inc – 56F803 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
DSP56F803/D
Rev. 13.0, 02/2004
56F803
Technical Data
56F803 16-bit Hybrid Controller
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Up to 64K × 16-bit words each of external
Program and Data memory
• 6-channel PWM module
• Hardware DO and REP loops
• Two 4-channel 12-bit ADCs
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• 31.5K × 16-bit words Program Flash
• 512 × 16-bit words Program RAM
• 4K × 16-bit words Data Flash
• 2K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Quadrature Decoder
• CAN 2.0 B module
• Serial Communication Interface (SCI)
• Serial Peripheral Interface (SPI)
• Up to two General Purpose Quad Timers
• JTAG/OnCE^TM port for debugging
• 16 shared GPIO lines
• 100–pin LQFP package
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
3
PWMA
EXTBOOT
RESET
IRQB
IRQA
6
VCAPC V_DD V_SS V_DDA
2
6
6*
V_SSA
A/D1
4
A/D2 ADC
4
VREF
Quadrature
Decoder 0 /
4
Quad Timer A
Interrupt
Controller
JTAG/
OnCE
Port
Digital Reg Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Program Memory
32252 x 16 Flash
512 x 16 SRAM
••
PAB
PDB
•
PLL
16-Bit
CLKO
Quad Timer B
Boot Flash
56800
XTAL
Quad Timer C
2048 x 16 Flash
XDB2
Core
Clock Gen
EXTAL
Quad Timer D
Data Memory
4096 x 16 Flash
2
2048 x 16 SRAM
CAN 2.0A/B
2
SCI
or
2
GPIO
COP/
•
CGDB
• _XAB1
• _XAB2
• _INTERRUPT
IPBB
•
CONTROLS CONTROLS
16
16
External ₆
Address Bus
A[00:05]
A[06:15] or
4
SPI
or
GPIO
Watchdog
Application-
Specific
Memory &
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
Switch
External
Data Bus
Switch
Bus
GPIO-E2:E3 &
10 _GPIO-A0:A7
D[00:15]
16
PS Select
DS Select
Peripherals
Control
WR Enable
*includes TCS pin which is reserved for factory use and is tied to VSS
RD Enable
Figure 1. 56F803 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
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