M68060 Datasheet, PDF (65/416 Pages) Motorola, Inc – M68060 User Manual

SECTION 3
INTEGER UNIT
This section describes the organization of the MC68060 integer unit and presents a brief
description of the associated registers. Refer to Section 4 Memory Management Unit for
details concerning the paged memory management unit (MMU) programming model and to
Section 6 Floating-Point Unit for details concerning the floating-point unit (FPU) program-
ming model.
3.1 INTEGER UNIT EXECUTION PIPELINES
The MC68060 integer unit execution pipelines are four-stage pipelines which perform final
instruction decode, effective address calculation, and execution or integer operations. The
operand execution pipelines (OEPs) are referred to individually as the primary OEP (pOEP)
and the secondary OEP (sOEP). Figure 3-1 shows the integer unit of the MC68060.
EXECUTION UNIT
INSTRUCTION FETCH UNIT
BRANCH
CACHE
IA
IAG
CALCULATE
INSTRUCTION IC
FETCH
EARLY ^IED
DECODE
FLOATING-
POINT
UNIT
EA
OC
FETCH
FP
EX
EXECUTE
INSTRUCTION
IB
BUFFER
pOEP
DECODE ^DS
sOEP
DECODE ^DS
EA
AG
CALCULATE
EA
OC
FETCH
INT
EX
EXECUTE
EA
AG
CALCULATE
EA
OC
FETCH
INT
EX
EXECUTE
INTEGER UNIT
DATA AVAILABLE
DA
WRITE-BACK
WB
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
CACHE
CONTROLLER
INSTRUCTION MEMORY UNIT
DATA
CACHE
CONTROLLER
DATA
ATC
DATA
CACHE
DATA MEMORY UNIT
ADDRESS
B
U
S
C
O
N
T
DATA
R
O
L
L
E
R
CONTROL
OPERAND DATA BUS
Figure 3-1. MC68060 Integer Unit Pipeline
MOTOROLA
M68060 USER’S MANUAL
3-1