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M68060 Datasheet, PDF (117/416 Pages) Motorola, Inc – M68060 User Manual | |||
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Caches
Read misses and write misses to copyback pages cause the cache controller to read a new
cache line from memory into the cache. If available, an invalid line in the selected set is
updated with the tag and data from memory. The line state then changes from invalid to valid
by setting the V-bit for the line. If all lines in the set are already valid or dirty, the pseudo
round-robin replacement algorithm is used to select one of the four lines and replace the tag
and data contents of the line with the new line information. Before replacement, dirty lines
are temporarily buffered and later copied back to memory after the new line has been read
from memory. Snoops always check both the push buffer and the cache. Figure 5-7 illus-
trates the three possible states for a data cache line, with the possible transitions caused by
either the processor or snooped accesses. Transitions are labeled with a capital letter, indi-
cating the previous state, followed by a number indicating the specific case listed in Table
5-3.
CI5â CINV
CI6â CPUSH
CV1âCPU READ MISS
CV2âCPU READ HIT
COPYBACK
INVALID
CI1âCPU READ MISS
CV5âCINV
CV6âCPUSH
CV7âSNOOP HIT
COPYBACK
VALID
CI3â CPU
WRITE MISS
CD5âCINV
CD6âCPUSH
CD7âSNOOP HIT
CD1âCPU
READ MISS
CV3âCPU WRITE MISS
CV4âCPU WRITE HIT
COPYBACK
DIRTY
CD2â CPU READ HIT
CD3âCPU WRITE MISS
CD4âCPU WRITE HIT
COPYBACK CACHING MODE
WI3âCPU WRITE MISS
WI5âCINV
WI6âCPUSH
WV1âCPU READ MISS
WV2âCPU READ HIT
WV3âCPU WRITE MISS
WV4âCPU WRITE HIT
WRITE-
THROUGH
INVALID
WI1â CPU READ MISS
WV5â CINV
WV6â CPUSH
WV7âSNOOP HIT
WRITE-
THROUGH
VALID
WRITETHROUGH CACHING MODE
Figure 5-7. Data Cache Line State Diagrams
5-18
M68060 USERâS MANUAL
MOTOROLA
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