M68060 Datasheet, PDF (295/416 Pages) Motorola, Inc – M68060 User Manual

IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
CLK
TCK
1
JTAG MODE
DEBUG MODE
2
3
4
5
6
7
8
9
10 11 12
13 14
CLK
2
3
4
PSHIFT
JTAG
TRST
JTAG
PDISABLE
TMS
PAPPLY
TDI
PTDI
STATE
SeIR
TLR
TLR
TLR
DISABLED
SHIFT
SHIFT APPLY ACTION
JTAG MUST BE IN TLR
NOTES:
1. Clock is shown at 2x TCK here for illustration. Any relationship may exist but 3 full rising edges of CLK should occur after JTAG
goes high and before PSHIFT or PDISABLE change.
2. When JTAG goes high, the MC68060 goes from "functional with JTAG" to "functional with DEBUG". When going to DEBUG
modes the JTAG package pins remap to:
TRST → PDISABLE
TDI → PTDI
TMS → PAPPLY
TCK → PSHIFT
ALL "P" signals internally negated when JTAG = low.
3. Hold TRST = H across boundary to prevent PAPPLY.
4. Hold TMS = H across boundary to keep JTAG in TLR.
5. After the boundary, PAPPLY must be negated before PDISABLE negates.
Figure 9-12. Transition from JTAG to Debug Mode Timing Diagram
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M68060 USER’S MANUAL
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