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MC9S12B128 Datasheet, PDF (50/128 Pages) Motorola, Inc – microcontroller unit (MCU) | |||
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Device User Guide â 9S12B128DGV1/D V01.11
2.1.1 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name
Function1
EXTAL
XTAL
RESET
TEST
VREGEN
XFC
BKGD
PAD[15:8]
PAD[07:00]
PA[7:0]
PB[7:0]
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PJ7
PJ6
PJ[1:0]
Pin Name
Function2
â
â
â
â
â
â
TAGHI
AN[15:8]
AN[07:00]
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
NOACC
IPIPE1
IPIPE0
ECLK
LSTRB
R/W
IRQ
XIRQ
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWJ7
KWJ6
KWJ[1:0]
Pin Name
Function
3
Pin Name
Function
4
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Internal Pull
Resistor
CTRL
Reset
State
Description
â
â
VDDPLL
â
â
Oscillator Pins
â
â
VDDR
External Reset
None None
â
â
N.A.
Test Input
â
â
VDDX
Voltage Regulator Enable Input
â
â
VDDPLL
PLL Loop Filter
MODC
â
VDDR
Always
Up
Up
Background Debug, Tag High, Mode
Input
â
â
Port AD Inputs, Analog Inputs
AN[15:8] of ATD
VDDA None None
â
â
Port AD Inputs, Analog Inputs
AN[7:0] of ATD
â
â
â
â
PUCR/
PUPAE
PUCR/
PUPBE
Port A I/O, Multiplexed Address/Data
Disabled
Port B I/O, Multiplexed Address/Data
XCLKS
â
PUCR/
PUPEE
Up Port E I/O, Access, Clock Select
MODB
â
MODA
â
While RESET pin Port E I/O, Pipe Status, Mode Input
is low:
Down
Port E I/O, Pipe Status, Mode Input
â
â
Mode Port E I/O, Bus Clock Output
TAGLO
â
depende Port E I/O, Byte Strobe, Tag Low
â
â
PUCR/
VDDR PUPEE
nt1 Port E I/O, R/W in expanded modes
â
â
Port E Input, Maskable Interrupt
â
â
Up
Port E Input, Non Maskable Interrupt
â
â
Port H I/O, Interrupt
â
â
Port H I/O, Interrupt
â
â
Port H I/O, Interrupt
â
â
â
â
PERH/
PPSH
Port H I/O, Interrupt
Disabled
Port H I/O, Interrupt
â
â
Port H I/O, Interrupt
â
â
Port H I/O, Interrupt
â
â
Port H I/O, Interrupt
SCL
SDA
â
â
Port J I/O, Interrupt, SCL of IIC,
â
VDDX
PERJ/
PPSJ
Up Port J I/O, Interrupt, SDA of IIC,
â
Port J I/O, Interrupts
50
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