MLP1N06CL Datasheet, PDF (5/6 Pages) Motorola, Inc – VOLTAGE CLAMPED CURRENT LIMITING MOSFET

1.0
0.7 D = 0.5
0.5
0.3
0.2
0.2
0.1
0.1
0.05
0.07
0.02
0.05
0.03
0.02
0.01
0.01
0.01
SINGLE PULSE
0.02 0.03 0.05 0.1
MLP1N06CL
R_θJC(t) = r(t) R_θJC
R_θJC(t) = 3.12°C/W Max
D Curves Apply for Power
Pulse Train Shown
RTeJa(pdkT) i–mTeCat=t1P(pk) _RθJC(t)
P(pk)
0.2 0.3 0.5 1.0 2.0 3.0 5.0 10
t, TIME (ms)
20 30 50
t1 _t2
DUTY CYCLE, D =t1/t2
100 200 300 500 1000
Figure 9. Thermal Response (MLP1N06CL)
PULSE GENERATOR
Rgen
50Ω
VDD
RL Vout
Vin
DUT
z = 50 Ω
50 Ω
td(on)
ton
tr
90%
td(off)
OUTPUT, Vout
10%
INVERTED
INPUT, Vin
50%
10%
PULSE WIDTH
toff
tf
90%
90%
50%
Figure 10. Switching Test Circuit
Figure 11. Switching Waveforms
ACTIVE CLAMPING
SMARTDISCRETES technology can provide on–chip real-
ization of the popular gate–to–source and gate–to–drain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, back–to–back diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each back–to–back
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gate–to–drain clamp voltages, several
voltage elements are strung together; the MLP1N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gate–to–source voltage clamp.
For the MLP1N06CL, the integrated gate–to–source voltage
elements provide greater than 2.0 kV electrostatic voltage
protection.
The avalanche voltage of the gate–to–drain voltage clamp
is set less than that of the power MOSFET device. As soon
as the drain–to–source voltage exceeds this avalanche volt-
age, the resulting gate–to–drain Zener current builds a gate
voltage across the gate–to–source impedance, turning on
the power device which then conducts the current. Since vir-
tually all of the current is carried by the power device, the
gate–to–drain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
drain–to–source sustaining voltage (Figure 7) effectively re-
moves the possibility of drain–to–source avalanche in the
power device.
The gate–to–drain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gate–to–drain clamped
conduction mode rather than in the more stressful gate–to–
source avalanche mode.
Motorola TMOS Power MOSFET Transistor Device Data
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