MCD212 Datasheet, PDF (35/87 Pages) Motorola, Inc – Video Decoder and System Controller(with JTAG)

P
VSYNC
CSYNC
(ODD FIELD)
623
624
625
1
2
3
4
5
310
CSYNC
(EVEN FIELD)
311
312
313
314
315
316
317
318
G
H
A/2
A
Figure 5–8. CSYNC Timing in the 50 Hz (FD = 0), Interlace Mode (SM = 1)
P
VSYNC
CSYNC
(ODD FIELD)
523
524
525
1
2
3
4
5
260
CSYNC
(EVEN FIELD)
261
262
263
264
265
266
267
268
Figure 5–9. CSYNC Timing in the 60 Hz (FD = 1), Interlace Mode (SM = 1)
5.4
SOFTWARE
The VDSC offers the possibility to fetch control information during vertical and horizontal retrace peri-
ods from the Image Control Area (ICA) and Dynamic Control Area (DCA), respectively. Each video
channel has its associated ICA and DCA. For channel 1 this is ICA1 and DCA1, and for channel 2 this
is ICA2 and DCA2. ICA/DCA control is identical and independent for both channels.
5.4.1
ICA Control
ICA control consists of fetching long–word instructions during the vertical retrace period. The ICA
pointers are indicated in Table 5–8.
Table 5–8. ICA Pointer Addresses
Interlace
Non–Interlace
Odd Field
(PA = 1)
Even Field
(PA = 0)
Channel 1 (ICA1)
h400
h400
h404
Channel 2 (ICA2)
h200400
h200400
h200404
NOTE: Odd and even fields are indicated by the PA bit in the CSR1R register.
5–6
MCD212
MOTOROLA